diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 691fdedeae3..7719bef94e6 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -26866,20 +26866,22 @@ static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) { static SDValue performFMaxNumCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) { - // This takes at least 3 instructions, so favor a library call when - // minimizing code size. - if (DAG.getMachineFunction().getFunction()->optForMinSize()) + if (Subtarget->useSoftFloat()) return SDValue(); - EVT VT = N->getValueType(0); - // TODO: Check for global or instruction-level "nnan". In that case, we // should be able to lower to FMAX/FMIN alone. // TODO: If an operand is already known to be a NaN or not a NaN, this // should be an optional swap and FMAX/FMIN. // TODO: Allow f64, vectors, and fminnum. - if (VT != MVT::f32 || !Subtarget->hasSSE1() || Subtarget->useSoftFloat()) + EVT VT = N->getValueType(0); + if (!(Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32))) + return SDValue(); + + // This takes at least 3 instructions, so favor a library call when operating + // on a scalar and minimizing code size. + if (!VT.isVector() && DAG.getMachineFunction().getFunction()->optForMinSize()) return SDValue(); SDValue Op0 = N->getOperand(0); @@ -26911,7 +26913,8 @@ static SDValue performFMaxNumCombine(SDNode *N, SelectionDAG &DAG, // If Op0 is a NaN, select Op1. Otherwise, select the max. If both operands // are NaN, the NaN value of Op1 is the result. - return DAG.getNode(ISD::SELECT, DL, VT, IsOp0Nan, Op1, Max); + auto SelectOpcode = VT.isVector() ? ISD::VSELECT : ISD::SELECT; + return DAG.getNode(SelectOpcode, DL, VT, IsOp0Nan, Op1, Max); } /// Do target-specific dag combines on X86ISD::FAND nodes. |
