diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 49 |
1 files changed, 16 insertions, 33 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 65af84c9513..2a270b54502 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -656,12 +656,11 @@ multiclass vextract_for_size<int Opcode, // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to // vextract_extract), we interesting only in patterns without mask, // intrinsics pattern match generated bellow. - defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst), + defm rr : AVX512_maskable<Opcode, MRMDestReg, To, (outs To.RC:$dst), (ins From.RC:$src1, u8imm:$idx), "vextract" # To.EltTypeName # "x" # To.NumElts, "$idx, $src1", "$src1, $idx", - [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1), - (iPTR imm)))]>, + (vextract_extract:$idx (From.VT From.RC:$src1), (iPTR imm))>, AVX512AIi8Base, EVEX; def mr : AVX512AIi8<Opcode, MRMDestMem, (outs), (ins To.MemOp:$dst, From.RC:$src1, u8imm:$idx), @@ -680,24 +679,6 @@ multiclass vextract_for_size<int Opcode, "$dst {${mask}}, $src1, $idx}", []>, EVEX_K, EVEX; } - - def : Pat<(To.VT (vselect To.KRCWM:$mask, - (vextract_extract:$ext (From.VT From.RC:$src1), - (iPTR imm)), - To.RC:$src0)), - (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts # - From.ZSuffix # "rrk") - To.RC:$src0, To.KRCWM:$mask, From.RC:$src1, - (EXTRACT_get_vextract_imm To.RC:$ext))>; - - def : Pat<(To.VT (vselect To.KRCWM:$mask, - (vextract_extract:$ext (From.VT From.RC:$src1), - (iPTR imm)), - To.ImmAllZerosV)), - (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts # - From.ZSuffix # "rrkz") - To.KRCWM:$mask, From.RC:$src1, - (EXTRACT_get_vextract_imm To.RC:$ext))>; } // Codegen pattern for the alternative types @@ -718,18 +699,20 @@ multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From, multiclass vextract_for_type<ValueType EltVT32, int Opcode128, ValueType EltVT64, int Opcode256> { - defm NAME # "32x4Z" : vextract_for_size<Opcode128, - X86VectorVTInfo<16, EltVT32, VR512>, - X86VectorVTInfo< 4, EltVT32, VR128X>, - vextract128_extract, - EXTRACT_get_vextract128_imm>, - EVEX_V512, EVEX_CD8<32, CD8VT4>; - defm NAME # "64x4Z" : vextract_for_size<Opcode256, - X86VectorVTInfo< 8, EltVT64, VR512>, - X86VectorVTInfo< 4, EltVT64, VR256X>, - vextract256_extract, - EXTRACT_get_vextract256_imm>, - VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>; + let Predicates = [HasAVX512] in { + defm NAME # "32x4Z" : vextract_for_size<Opcode128, + X86VectorVTInfo<16, EltVT32, VR512>, + X86VectorVTInfo< 4, EltVT32, VR128X>, + vextract128_extract, + EXTRACT_get_vextract128_imm>, + EVEX_V512, EVEX_CD8<32, CD8VT4>; + defm NAME # "64x4Z" : vextract_for_size<Opcode256, + X86VectorVTInfo< 8, EltVT64, VR512>, + X86VectorVTInfo< 4, EltVT64, VR256X>, + vextract256_extract, + EXTRACT_get_vextract256_imm>, + VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>; + } let Predicates = [HasVLX] in defm NAME # "32x4Z256" : vextract_for_size<Opcode128, X86VectorVTInfo< 8, EltVT32, VR256X>, |
