diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86Schedule.td | 1 |
2 files changed, 6 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 160401cdf7a..053c07ad39c 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -1210,12 +1210,12 @@ def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; } // isCodeGenOnly = 1, ForceDisassemble = 1 } // mayLoad, SchedRW -let mayStore = 1, mayLoad = 1, SchedRW = [WriteRMW] in { +let mayStore = 1, mayLoad = 1, SchedRW = [WriteCopy] in { def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>, OpSize16; def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>, OpSize32, Requires<[Not64BitMode]>; -} // mayStore, mayLoad, WriteRMW +} // mayStore, mayLoad, SchedRW let mayStore = 1, SchedRW = [WriteStore] in { def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, @@ -1243,7 +1243,7 @@ def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), Requires<[Not64BitMode]>; } // mayStore, SchedRW -let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { +let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in { def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>, OpSize16; def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>, @@ -1302,7 +1302,7 @@ def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; } // isCodeGenOnly = 1, ForceDisassemble = 1 } // mayLoad, SchedRW -let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in +let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>, OpSize32, Requires<[In64BitMode]>; let mayStore = 1, SchedRW = [WriteStore] in { @@ -1314,7 +1314,7 @@ def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; } // isCodeGenOnly = 1, ForceDisassemble = 1 } // mayStore, SchedRW -let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { +let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in { def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>, OpSize32, Requires<[In64BitMode]>; } // mayLoad, mayStore, SchedRW diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td index 40884221d1f..39df5e74b68 100644 --- a/llvm/lib/Target/X86/X86Schedule.td +++ b/llvm/lib/Target/X86/X86Schedule.td @@ -107,6 +107,7 @@ def WriteLoad : SchedWrite; def WriteStore : SchedWrite; def WriteStoreNT : SchedWrite; def WriteMove : SchedWrite; +def WriteCopy : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy // Arithmetic. defm WriteALU : X86SchedWritePair; // Simple integer ALU op. |
