diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/IA64/IA64.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/IA64/IA64InstrInfo.td | 19 | ||||
| -rw-r--r-- | llvm/lib/Target/IA64/IA64RegisterInfo.td | 4 |
3 files changed, 18 insertions, 6 deletions
diff --git a/llvm/lib/Target/IA64/IA64.td b/llvm/lib/Target/IA64/IA64.td index 50da45e756f..85c431204d0 100644 --- a/llvm/lib/Target/IA64/IA64.td +++ b/llvm/lib/Target/IA64/IA64.td @@ -47,6 +47,7 @@ def IA64 : Target { // r1, // global data pointer (GP) - XXX NOT callee saved, we do it ourselves // r12, // memory stack pointer (SP)- XXX NOT callee saved, we do it ourselves +// rp, // return branch register (rp/b0) - we do this ourselves // **** r13 (thread pointer) we do not touch, ever. it's not here. ****// //r15, // our frame pointer (FP) diff --git a/llvm/lib/Target/IA64/IA64InstrInfo.td b/llvm/lib/Target/IA64/IA64InstrInfo.td index 4a349b0a9a9..28462f39169 100644 --- a/llvm/lib/Target/IA64/IA64InstrInfo.td +++ b/llvm/lib/Target/IA64/IA64InstrInfo.td @@ -23,7 +23,7 @@ def s8imm : Operand<i8> { def s14imm : Operand<i64> { let PrintMethod = "printS14ImmOperand"; } -def s22imm : Operand<i32> { +def s22imm : Operand<i64> { let PrintMethod = "printS22ImmOperand"; } def u64imm : Operand<i64> { @@ -116,7 +116,12 @@ def MOVL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, s64imm:$imm), def ADDL_GA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, globaladdress:$imm), "addl $dst = $imm, $src1;;", []>; - + +// hmm +def ADDL_EA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, calltarget:$imm), + "addl $dst = $imm, $src1;;", + []>; + def SUB : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "sub $dst = $src1, $src2;;", [(set GR:$dst, (sub GR:$src1, GR:$src2))]>; @@ -639,7 +644,7 @@ let isTerminator = 1, isBranch = 1 in { "($qp) br.cond.sptk $dst;;">; } -let isCall = 1, isTerminator = 1, isBranch = 1, +let isCall = 1, /* isTerminator = 1, isBranch = 1, */ Uses = [out0,out1,out2,out3,out4,out5,out6,out7], // all calls clobber non-callee-saved registers, and for now, they are these: Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24, @@ -659,8 +664,14 @@ let isCall = 1, isTerminator = 1, isBranch = 1, def BRCALL: RawForm<0x03, 0xb0, (ops calltarget:$dst), "br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs? // new daggy stuff! - def BRCALL_IPREL : RawForm<0x03, 0xb0, (ops calltarget:$dst, variable_ops), + +// calls a globaladdress + def BRCALL_IPREL_GA : RawForm<0x03, 0xb0, (ops calltarget:$dst, variable_ops), + "br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs? +// calls an externalsymbol + def BRCALL_IPREL_ES : RawForm<0x03, 0xb0, (ops calltarget:$dst, variable_ops), "br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs? +// calls through a function descriptor def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (ops GR:$branchreg, variable_ops), "br.call.sptk rp = $branchreg;;">; // FIXME: teach llvm about branch regs? def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst), diff --git a/llvm/lib/Target/IA64/IA64RegisterInfo.td b/llvm/lib/Target/IA64/IA64RegisterInfo.td index 03aba454635..936f123745c 100644 --- a/llvm/lib/Target/IA64/IA64RegisterInfo.td +++ b/llvm/lib/Target/IA64/IA64RegisterInfo.td @@ -235,8 +235,8 @@ def B6 : GR<0, "b6">; def GR : RegisterClass<"IA64", [i64], 64, [ -//FIXME!: for readability, we don't want the out registers to be the first -// ones allocated +//FIXME!: for both readability and performance, we don't want the out +// registers to be the first ones allocated out7, out6, out5, out4, out3, out2, out1, out0, r3, r8, r9, r10, r11, r14, |
