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-rw-r--r--llvm/lib/Target/AArch64/AArch64.td4
-rw-r--r--llvm/lib/Target/AArch64/AArch64Subtarget.h2
2 files changed, 0 insertions, 6 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 6c4bba1c496..5c66748cee6 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -102,9 +102,6 @@ def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
"Disable latency scheduling heuristic">;
-def FeatureUseRSqrt : SubtargetFeature<
- "use-reverse-square-root", "UseRSqrt", "true", "Use reverse square root">;
-
//===----------------------------------------------------------------------===//
// Architectures.
//
@@ -225,7 +222,6 @@ def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
FeatureNEON,
FeaturePerfMon,
FeaturePostRAScheduler,
- FeatureUseRSqrt,
FeatureZCZeroing
]>;
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index ee07fec2e75..0ab823b4e6b 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -82,7 +82,6 @@ protected:
bool UseAlternateSExtLoadCVTF32Pattern = false;
bool HasMacroOpFusion = false;
bool DisableLatencySchedHeuristic = false;
- bool UseRSqrt = false;
uint8_t MaxInterleaveFactor = 2;
uint8_t VectorInsertExtractBaseCost = 3;
uint16_t CacheLineSize = 0;
@@ -191,7 +190,6 @@ public:
return UseAlternateSExtLoadCVTF32Pattern;
}
bool hasMacroOpFusion() const { return HasMacroOpFusion; }
- bool useRSqrt() const { return UseRSqrt; }
unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
unsigned getVectorInsertExtractBaseCost() const {
return VectorInsertExtractBaseCost;
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