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-rw-r--r--llvm/lib/Object/ELFObjectFile.cpp18
-rw-r--r--llvm/lib/Support/ARMAttributeParser.cpp17
-rw-r--r--llvm/lib/Support/ARMBuildAttrs.cpp1
-rw-r--r--llvm/lib/Support/ARMTargetParser.cpp7
-rw-r--r--llvm/lib/Support/Triple.cpp2
-rw-r--r--llvm/lib/Target/ARM/ARM.td24
-rw-r--r--llvm/lib/Target/ARM/ARMPredicates.td12
-rw-r--r--llvm/lib/Target/ARM/ARMSubtarget.h9
-rw-r--r--llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp9
9 files changed, 96 insertions, 3 deletions
diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp
index 1c3469b5971..c7b71579304 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -230,6 +230,24 @@ SubtargetFeatures ELFObjectFileBase::getARMFeatures() const {
}
}
+ if (Attributes.hasAttribute(ARMBuildAttrs::MVE_arch)) {
+ switch(Attributes.getAttributeValue(ARMBuildAttrs::MVE_arch)) {
+ default:
+ break;
+ case ARMBuildAttrs::Not_Allowed:
+ Features.AddFeature("mve", false);
+ Features.AddFeature("mve.fp", false);
+ break;
+ case ARMBuildAttrs::AllowMVEInteger:
+ Features.AddFeature("mve.fp", false);
+ Features.AddFeature("mve");
+ break;
+ case ARMBuildAttrs::AllowMVEIntegerAndFloat:
+ Features.AddFeature("mve.fp");
+ break;
+ }
+ }
+
if (Attributes.hasAttribute(ARMBuildAttrs::DIV_use)) {
switch(Attributes.getAttributeValue(ARMBuildAttrs::DIV_use)) {
default:
diff --git a/llvm/lib/Support/ARMAttributeParser.cpp b/llvm/lib/Support/ARMAttributeParser.cpp
index 0b7db2f2f72..08b939a8734 100644
--- a/llvm/lib/Support/ARMAttributeParser.cpp
+++ b/llvm/lib/Support/ARMAttributeParser.cpp
@@ -37,6 +37,7 @@ ARMAttributeParser::DisplayRoutines[] = {
ATTRIBUTE_HANDLER(FP_arch),
ATTRIBUTE_HANDLER(WMMX_arch),
ATTRIBUTE_HANDLER(Advanced_SIMD_arch),
+ ATTRIBUTE_HANDLER(MVE_arch),
ATTRIBUTE_HANDLER(PCS_config),
ATTRIBUTE_HANDLER(ABI_PCS_R9_use),
ATTRIBUTE_HANDLER(ABI_PCS_RW_data),
@@ -132,7 +133,9 @@ void ARMAttributeParser::CPU_arch(AttrType Tag, const uint8_t *Data,
static const char *const Strings[] = {
"Pre-v4", "ARM v4", "ARM v4T", "ARM v5T", "ARM v5TE", "ARM v5TEJ", "ARM v6",
"ARM v6KZ", "ARM v6T2", "ARM v6K", "ARM v7", "ARM v6-M", "ARM v6S-M",
- "ARM v7E-M", "ARM v8"
+ "ARM v7E-M", "ARM v8", nullptr,
+ "ARM v8-M Baseline", "ARM v8-M Mainline", nullptr, nullptr, nullptr,
+ "ARM v8.1-M Mainline"
};
uint64_t Value = ParseInteger(Data, Offset);
@@ -213,6 +216,18 @@ void ARMAttributeParser::Advanced_SIMD_arch(AttrType Tag, const uint8_t *Data,
PrintAttribute(Tag, Value, ValueDesc);
}
+void ARMAttributeParser::MVE_arch(AttrType Tag, const uint8_t *Data,
+ uint32_t &Offset) {
+ static const char *const Strings[] = {
+ "Not Permitted", "MVE integer", "MVE integer and float"
+ };
+
+ uint64_t Value = ParseInteger(Data, Offset);
+ StringRef ValueDesc =
+ (Value < array_lengthof(Strings)) ? Strings[Value] : nullptr;
+ PrintAttribute(Tag, Value, ValueDesc);
+}
+
void ARMAttributeParser::PCS_config(AttrType Tag, const uint8_t *Data,
uint32_t &Offset) {
static const char *const Strings[] = {
diff --git a/llvm/lib/Support/ARMBuildAttrs.cpp b/llvm/lib/Support/ARMBuildAttrs.cpp
index f5fb64bb7ba..d0c4fb792cb 100644
--- a/llvm/lib/Support/ARMBuildAttrs.cpp
+++ b/llvm/lib/Support/ARMBuildAttrs.cpp
@@ -28,6 +28,7 @@ const struct {
{ ARMBuildAttrs::FP_arch, "Tag_FP_arch" },
{ ARMBuildAttrs::WMMX_arch, "Tag_WMMX_arch" },
{ ARMBuildAttrs::Advanced_SIMD_arch, "Tag_Advanced_SIMD_arch" },
+ { ARMBuildAttrs::MVE_arch, "Tag_MVE_arch" },
{ ARMBuildAttrs::PCS_config, "Tag_PCS_config" },
{ ARMBuildAttrs::ABI_PCS_R9_use, "Tag_ABI_PCS_R9_use" },
{ ARMBuildAttrs::ABI_PCS_RW_data, "Tag_ABI_PCS_RW_data" },
diff --git a/llvm/lib/Support/ARMTargetParser.cpp b/llvm/lib/Support/ARMTargetParser.cpp
index 02f0d95ff27..a33f602e532 100644
--- a/llvm/lib/Support/ARMTargetParser.cpp
+++ b/llvm/lib/Support/ARMTargetParser.cpp
@@ -77,6 +77,7 @@ unsigned ARM::parseArchVersion(StringRef Arch) {
case ArchKind::ARMV8R:
case ArchKind::ARMV8MBaseline:
case ArchKind::ARMV8MMainline:
+ case ArchKind::ARMV8_1MMainline:
return 8;
case ArchKind::INVALID:
return 0;
@@ -93,6 +94,7 @@ ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
case ArchKind::ARMV7EM:
case ArchKind::ARMV8MMainline:
case ArchKind::ARMV8MBaseline:
+ case ArchKind::ARMV8_1MMainline:
return ProfileKind::M;
case ArchKind::ARMV7R:
case ArchKind::ARMV8R:
@@ -151,6 +153,7 @@ StringRef ARM::getArchSynonym(StringRef Arch) {
.Case("v8r", "v8-r")
.Case("v8m.base", "v8-m.base")
.Case("v8m.main", "v8-m.main")
+ .Case("v8.1m.main", "v8.1-m.main")
.Default(Arch);
}
@@ -164,6 +167,10 @@ bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) {
// higher. We also have to make sure to disable fp16 when vfp4 is disabled,
// as +vfp4 implies +fp16 but -vfp4 does not imply -fp16.
switch (FPUNames[FPUKind].FPUVer) {
+ case FPUVersion::VFPV5_FULLFP16:
+ Features.push_back("+fp-armv8");
+ Features.push_back("+fullfp16");
+ break;
case FPUVersion::VFPV5:
Features.push_back("+fp-armv8");
break;
diff --git a/llvm/lib/Support/Triple.cpp b/llvm/lib/Support/Triple.cpp
index caf39a761d7..eacfe3b6bf0 100644
--- a/llvm/lib/Support/Triple.cpp
+++ b/llvm/lib/Support/Triple.cpp
@@ -625,6 +625,8 @@ static Triple::SubArchType parseSubArch(StringRef SubArchName) {
return Triple::ARMSubArch_v8m_baseline;
case ARM::ArchKind::ARMV8MMainline:
return Triple::ARMSubArch_v8m_mainline;
+ case ARM::ArchKind::ARMV8_1MMainline:
+ return Triple::ARMSubArch_v8_1m_mainline;
default:
return Triple::NoSubArch;
}
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 62cd79c9347..5671c0bd831 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -498,6 +498,19 @@ def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
"Support ARM v8.5a instructions",
[HasV8_4aOps, FeatureSB]>;
+def HasV8_1MMainlineOps : SubtargetFeature<
+ "v8.1m.main", "HasV8_1MMainlineOps", "true",
+ "Support ARM v8-1M Mainline instructions",
+ [HasV8MMainlineOps]>;
+def HasMVEIntegerOps : SubtargetFeature<
+ "mve", "HasMVEIntegerOps", "true",
+ "Support M-Class Vector Extension with integer ops",
+ [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>;
+def HasMVEFloatOps : SubtargetFeature<
+ "mve.fp", "HasMVEFloatOps", "true",
+ "Support M-Class Vector Extension with integer and floating ops",
+ [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>;
+
//===----------------------------------------------------------------------===//
// ARM Processor subtarget features.
//
@@ -783,6 +796,17 @@ def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
FeatureAcquireRelease,
FeatureMClass]>;
+def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline",
+ [HasV8_1MMainlineOps,
+ FeatureNoARM,
+ ModeThumb,
+ FeatureDB,
+ FeatureHWDivThumb,
+ Feature8MSecExt,
+ FeatureAcquireRelease,
+ FeatureMClass,
+ FeatureRAS]>;
+
// Aliases
def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>;
def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>;
diff --git a/llvm/lib/Target/ARM/ARMPredicates.td b/llvm/lib/Target/ARM/ARMPredicates.td
index ab4ed3936ab..1df22e60be5 100644
--- a/llvm/lib/Target/ARM/ARMPredicates.td
+++ b/llvm/lib/Target/ARM/ARMPredicates.td
@@ -26,6 +26,15 @@ def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">,
def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">,
AssemblerPredicate<"HasV8MMainlineOps",
"armv8m.main">;
+def HasV8_1MMainline : Predicate<"Subtarget->hasV8_1MMainlineOps()">,
+ AssemblerPredicate<"HasV8_1MMainlineOps",
+ "armv8.1m.main">;
+def HasMVEInt : Predicate<"Subtarget->hasMVEIntegerOps()">,
+ AssemblerPredicate<"HasMVEIntegerOps",
+ "mve">;
+def HasMVEFloat : Predicate<"Subtarget->hasMVEFloatOps()">,
+ AssemblerPredicate<"HasMVEFloatOps",
+ "mve.fp">;
def HasFPRegs : Predicate<"Subtarget->hasFPRegs()">,
AssemblerPredicate<"FeatureFPRegs",
"fp registers">;
@@ -35,6 +44,9 @@ def HasFPRegs16 : Predicate<"Subtarget->hasFPRegs16()">,
def HasFPRegs64 : Predicate<"Subtarget->hasFPRegs64()">,
AssemblerPredicate<"FeatureFPRegs64",
"64-bit fp registers">;
+def HasFPRegsV8_1M : Predicate<"Subtarget->hasFPRegs() && Subtarget->hasV8_1MMainlineOps()">,
+ AssemblerPredicate<"FeatureFPRegs,HasV8_1MMainlineOps",
+ "armv8.1m.main with FP or MVE">;
def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 03bea3572ce..8123ef6224b 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -110,7 +110,8 @@ protected:
ARMv8a,
ARMv8mBaseline,
ARMv8mMainline,
- ARMv8r
+ ARMv8r,
+ ARMv81mMainline,
};
public:
@@ -157,6 +158,9 @@ protected:
bool HasV8_5aOps = false;
bool HasV8MBaselineOps = false;
bool HasV8MMainlineOps = false;
+ bool HasV8_1MMainlineOps = false;
+ bool HasMVEIntegerOps = false;
+ bool HasMVEFloatOps = false;
/// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
/// floating point ISAs are supported.
@@ -569,6 +573,9 @@ public:
bool hasV8_5aOps() const { return HasV8_5aOps; }
bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
+ bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; }
+ bool hasMVEIntegerOps() const { return HasMVEIntegerOps; }
+ bool hasMVEFloatOps() const { return HasMVEFloatOps; }
bool hasFPRegs() const { return HasFPRegs; }
bool hasFPRegs16() const { return HasFPRegs16; }
bool hasFPRegs64() const { return HasFPRegs64; }
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
index 9502a5d7c39..b863517c0cc 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
@@ -124,7 +124,9 @@ static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) {
if (STI.hasFeature(ARM::FeatureRClass))
return ARMBuildAttrs::v8_R;
return ARMBuildAttrs::v8_A;
- } else if (STI.hasFeature(ARM::HasV8MMainlineOps))
+ } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps))
+ return ARMBuildAttrs::v8_1_M_Main;
+ else if (STI.hasFeature(ARM::HasV8MMainlineOps))
return ARMBuildAttrs::v8_M_Main;
else if (STI.hasFeature(ARM::HasV7Ops)) {
if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP))
@@ -262,6 +264,11 @@ void ARMTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
if (STI.hasFeature(ARM::FeatureMP))
emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
+ if (STI.hasFeature(ARM::HasMVEFloatOps))
+ emitAttribute(ARMBuildAttrs::MVE_arch, ARMBuildAttrs::AllowMVEIntegerAndFloat);
+ else if (STI.hasFeature(ARM::HasMVEIntegerOps))
+ emitAttribute(ARMBuildAttrs::MVE_arch, ARMBuildAttrs::AllowMVEInteger);
+
// Hardware divide in ARM mode is part of base arch, starting from ARMv8.
// If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
// It is not possible to produce DisallowDIV: if hwdiv is present in the base
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