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-rwxr-xr-xllvm/lib/Target/X86/X86SchedBroadwell.td6
-rw-r--r--llvm/lib/Target/X86/X86SchedHaswell.td2
-rw-r--r--llvm/lib/Target/X86/X86SchedSkylakeClient.td2
-rwxr-xr-xllvm/lib/Target/X86/X86SchedSkylakeServer.td2
-rw-r--r--llvm/lib/Target/X86/X86ScheduleZnver1.td24
5 files changed, 18 insertions, 18 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index bba524a6893..a64fe0c28f5 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -880,7 +880,7 @@ def: InstRW<[BWWriteResGroup9], (instregex "INC(16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "INC8r")>;
def: InstRW<[BWWriteResGroup9], (instregex "LAHF")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV(16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "MOV8ri(_alt)?")>;
+def: InstRW<[BWWriteResGroup9], (instregex "MOV8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr32")>;
@@ -1217,7 +1217,7 @@ def: InstRW<[BWWriteResGroup27], (instregex "COMISSrr")>;
def: InstRW<[BWWriteResGroup27], (instregex "CVTDQ2PSrr")>;
def: InstRW<[BWWriteResGroup27], (instregex "CVTPS2DQrr")>;
def: InstRW<[BWWriteResGroup27], (instregex "CVTTPS2DQrr")>;
-def: InstRW<[BWWriteResGroup27], (instregex "IMUL(32|64)rr(i8)?")>;
+def: InstRW<[BWWriteResGroup27], (instregex "IMUL(32|64)rr")>;
def: InstRW<[BWWriteResGroup27], (instregex "IMUL8r")>;
def: InstRW<[BWWriteResGroup27], (instregex "LZCNT(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup27], (instregex "MAX(C?)PDrr")>;
@@ -1298,7 +1298,7 @@ def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup27_16], (instregex "IMUL16rr(i8)?")>;
+def: InstRW<[BWWriteResGroup27_16], (instregex "IMUL16rr")>;
def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
let Latency = 3;
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index a48c8716bf9..1a79f6e7131 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -1439,7 +1439,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "INC(16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "INC8r")>;
def: InstRW<[HWWriteResGroup10], (instregex "LAHF")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOV(16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "MOV8ri(_alt)?")>;
+def: InstRW<[HWWriteResGroup10], (instregex "MOV8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOV8rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index a29464280ab..97a9c9b0c67 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -878,7 +878,7 @@ def: InstRW<[SKLWriteResGroup10], (instregex "INC(16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "INC8r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "LAHF")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOV(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "MOV8ri(_alt)?")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "MOV8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOV8rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index b7892c4a2a2..05b6da035af 100755
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -1308,7 +1308,7 @@ def: InstRW<[SKXWriteResGroup10], (instregex "INC(16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "INC8r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "LAHF")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV(16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "MOV8ri(_alt)?")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "MOV8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV8rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index 5b12587abfe..4ed8e7cf588 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -1594,21 +1594,21 @@ def : InstRW<[ZnWriteVDIVPDYLd], (instregex "VDIVPDYrm")>;
def ZnWriteVRCPPSr : SchedWriteRes<[ZnFPU01]> {
let Latency = 5;
}
-def : InstRW<[ZnWriteVRCPPSr], (instregex "VRCPPSYr(_Int)?")>;
+def : InstRW<[ZnWriteVRCPPSr], (instregex "VRCPPSYr")>;
// y,m256.
def ZnWriteVRCPPSLd : SchedWriteRes<[ZnAGU, ZnFPU01]> {
let Latency = 12;
let NumMicroOps = 3;
}
-def : InstRW<[ZnWriteVRCPPSLd], (instregex "VRCPPSYm(_Int)?")>;
+def : InstRW<[ZnWriteVRCPPSLd], (instregex "VRCPPSYm")>;
// ROUND SS/SD PS/PD.
// v,v,i.
def ZnWriteROUNDr : SchedWriteRes<[ZnFPU3]> {
let Latency = 4;
}
-def : InstRW<[ZnWriteROUNDr], (instregex "(V?)ROUND(Y?)(S|P)(S|D)r(_Int)?")>;
+def : InstRW<[ZnWriteROUNDr], (instregex "(V?)ROUND(Y?)(S|P)(S|D)r")>;
// VFMADD.
// v,v,v.
@@ -1619,7 +1619,7 @@ def : InstRW<[ZnWriteFMADDr],
(instregex
"VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(213|132|231)(Y?)r",
"VF(N?)M(ADD|SUB)(132|231|213)S(S|D)r",
- "VF(N?)M(ADD|SUB)S(S|D)4rr(_Int)?",
+ "VF(N?)M(ADD|SUB)S(S|D)4rr",
"VF(N?)M(ADD|SUB)P(S|D)4(Y?)rr")>;
// v,v,m.
@@ -1631,7 +1631,7 @@ def : InstRW<[ZnWriteFMADDm],
(instregex
"VF(N?)M(ADD|SUB|ADDSUB|SUBADD)(213|132|231)P(S|D)(Y?)m",
"VF(N?)M(ADD|SUB)(132|231|213)S(S|D)m",
- "VF(N?)M(ADD|SUB)S(S|D)4(rm|mr)(_Int)?",
+ "VF(N?)M(ADD|SUB)S(S|D)4(rm|mr)",
"VF(N?)M(ADD|SUB)P(S|D)4(Y?)(rm|mr)")>;
// v,m,i.
@@ -1639,7 +1639,7 @@ def ZnWriteROUNDm : SchedWriteRes<[ZnAGU, ZnFPU3]> {
let Latency = 11;
let NumMicroOps = 2;
}
-def : InstRW<[ZnWriteROUNDm], (instregex "(V?)ROUND(Y?)(S|P)(S|D)m(_Int)?")>;
+def : InstRW<[ZnWriteROUNDm], (instregex "(V?)ROUND(Y?)(S|P)(S|D)m")>;
// DPPS.
// x,x,i / v,v,v,i.
@@ -1692,14 +1692,14 @@ def : InstRW<[ZnWriteVSQRTPDYLd], (instregex "VSQRTPDYm")>;
def ZnWriteRSQRTSSr : SchedWriteRes<[ZnFPU02]> {
let Latency = 5;
}
-def : InstRW<[ZnWriteRSQRTSSr], (instregex "(V?)RSQRTSS(Y?)r(_Int)?")>;
+def : InstRW<[ZnWriteRSQRTSSr], (instregex "(V?)RSQRTSS(Y?)r")>;
// RSQRTPS
// x,x.
def ZnWriteRSQRTPSr : SchedWriteRes<[ZnFPU01]> {
let Latency = 5;
}
-def : InstRW<[ZnWriteRSQRTPSr], (instregex "(V?)RSQRTPS(Y?)r(_Int)?")>;
+def : InstRW<[ZnWriteRSQRTPSr], (instregex "(V?)RSQRTPS(Y?)r")>;
// RSQRTSSm
// x,m128.
@@ -1708,14 +1708,14 @@ def ZnWriteRSQRTSSLd: SchedWriteRes<[ZnAGU, ZnFPU02]> {
let NumMicroOps = 2;
let ResourceCycles = [1,2];
}
-def : InstRW<[ZnWriteRSQRTSSLd], (instregex "(V?)RSQRTSSm(_Int)?")>;
+def : InstRW<[ZnWriteRSQRTSSLd], (instregex "(V?)RSQRTSSm")>;
// RSQRTPSm
def ZnWriteRSQRTPSLd : SchedWriteRes<[ZnAGU, ZnFPU01]> {
let Latency = 12;
let NumMicroOps = 2;
}
-def : InstRW<[ZnWriteRSQRTPSLd], (instregex "(V?)RSQRTPSm(_Int)?")>;
+def : InstRW<[ZnWriteRSQRTPSLd], (instregex "(V?)RSQRTPSm")>;
// RSQRTPS 256.
// y,y.
@@ -1724,14 +1724,14 @@ def ZnWriteRSQRTPSYr : SchedWriteRes<[ZnFPU01]> {
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def : InstRW<[ZnWriteRSQRTPSYr], (instregex "VRSQRTPSYr(_Int)?")>;
+def : InstRW<[ZnWriteRSQRTPSYr], (instregex "VRSQRTPSYr")>;
// y,m256.
def ZnWriteRSQRTPSYLd : SchedWriteRes<[ZnAGU, ZnFPU01]> {
let Latency = 12;
let NumMicroOps = 2;
}
-def : InstRW<[ZnWriteRSQRTPSYLd], (instregex "VRSQRTPSYm(_Int)?")>;
+def : InstRW<[ZnWriteRSQRTPSYLd], (instregex "VRSQRTPSYm")>;
//-- Logic instructions --//
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