diff options
Diffstat (limited to 'llvm/lib')
25 files changed, 34 insertions, 30 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 646867993ce..284b984f0a1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -5735,7 +5735,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, } SmallVector<SDValue, 4> InVals; - Chain = LowerCall(Chain, Callee, RetTy, CallConv, isVarArg, isTailCall, + Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, Outs, Ins, dl, DAG, InVals); // Verify that the target's LowerCall behaved as expected. diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 0c8e58a0947..3e42be3132f 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -895,7 +895,7 @@ void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter /// nodes. SDValue -ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, +ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index e4c32f952e4..a408943c508 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -317,7 +317,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp index 980db130efa..0bbe5671041 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp @@ -219,7 +219,7 @@ static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) { #include "AlphaGenCallingConv.inc" SDValue -AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, +AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.h b/llvm/lib/Target/Alpha/AlphaISelLowering.h index 9f73d77dcf3..0f17025b774 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.h +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.h @@ -120,7 +120,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/llvm/lib/Target/Blackfin/BlackfinISelLowering.cpp b/llvm/lib/Target/Blackfin/BlackfinISelLowering.cpp index 0e729b86181..269707a8e82 100644 --- a/llvm/lib/Target/Blackfin/BlackfinISelLowering.cpp +++ b/llvm/lib/Target/Blackfin/BlackfinISelLowering.cpp @@ -272,7 +272,6 @@ BlackfinTargetLowering::LowerReturn(SDValue Chain, SDValue BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee, - const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/Blackfin/BlackfinISelLowering.h b/llvm/lib/Target/Blackfin/BlackfinISelLowering.h index 147f414f43e..5f399103f15 100644 --- a/llvm/lib/Target/Blackfin/BlackfinISelLowering.h +++ b/llvm/lib/Target/Blackfin/BlackfinISelLowering.h @@ -63,7 +63,7 @@ namespace llvm { DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp index b6a8faddc3a..fe0f0196465 100644 --- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp @@ -1138,7 +1138,7 @@ static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) { } SDValue -SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, +SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.h b/llvm/lib/Target/CellSPU/SPUISelLowering.h index 3625f916d07..3c511772680 100644 --- a/llvm/lib/Target/CellSPU/SPUISelLowering.h +++ b/llvm/lib/Target/CellSPU/SPUISelLowering.h @@ -156,7 +156,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp index d948e6f527d..ef81f51229f 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -271,7 +271,7 @@ MSP430TargetLowering::LowerFormalArguments(SDValue Chain, } SDValue -MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,const Type *RetTy, +MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.h b/llvm/lib/Target/MSP430/MSP430ISelLowering.h index c4b70b16507..87a790b047b 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelLowering.h +++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.h @@ -153,7 +153,7 @@ namespace llvm { DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 4426e761f8c..6d932ec04da 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -684,7 +684,7 @@ static bool CC_MipsO32(unsigned ValNo, EVT ValVT, /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. /// TODO: isVarArg, isTailCall. SDValue -MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, +MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h index c8256e7430a..d8b453ceb25 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.h +++ b/llvm/lib/Target/Mips/MipsISelLowering.h @@ -116,7 +116,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/PIC16/PIC16ISelLowering.cpp b/llvm/lib/Target/PIC16/PIC16ISelLowering.cpp index d9add7f398d..7754a4f1458 100644 --- a/llvm/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/llvm/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -1353,7 +1353,7 @@ GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain, } SDValue -PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, +PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/PIC16/PIC16ISelLowering.h b/llvm/lib/Target/PIC16/PIC16ISelLowering.h index e67f8bc8126..de1452015f6 100644 --- a/llvm/lib/Target/PIC16/PIC16ISelLowering.h +++ b/llvm/lib/Target/PIC16/PIC16ISelLowering.h @@ -142,7 +142,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 310ace8e26e..2a4fb024bb6 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2674,7 +2674,7 @@ PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, } SDValue -PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, +PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index 4bf70b865da..9c390ac1014 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -430,7 +430,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index d5d61ead993..e67002a7dbe 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -250,7 +250,7 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain, } SDValue -SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, +SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.h b/llvm/lib/Target/Sparc/SparcISelLowering.h index 8765de83d91..2ee73c1ac90 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.h +++ b/llvm/lib/Target/Sparc/SparcISelLowering.h @@ -85,7 +85,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 8146666974b..f7405a52deb 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -249,7 +249,6 @@ SystemZTargetLowering::LowerFormalArguments(SDValue Chain, SDValue SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee, - const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h index ee06957b82d..36ff994d031 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h @@ -124,7 +124,7 @@ namespace llvm { DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 228244f06bf..d05de21be3d 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1778,7 +1778,7 @@ EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, } SDValue -X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, +X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, @@ -1791,8 +1791,8 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, if (isTailCall) // Check if it's really possible to do a tail call. - isTailCall = IsEligibleForTailCallOptimization(Callee, RetTy, CallConv, - isVarArg, Outs, Ins, DAG); + isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, + Outs, Ins, DAG); assert(!(isVarArg && CallConv == CallingConv::Fast) && "Var args not supported with calling convention fastcc"); @@ -2247,7 +2247,6 @@ unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, /// optimization should implement this function. bool X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, - const Type *RetTy, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, @@ -2329,7 +2328,14 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, return true; // If the return types match, then it's safe. - return CallerRetTy == RetTy; + // Don't tail call optimize recursive call. + GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); + if (!G) return false; // FIXME: common external symbols? + if (const Function *CalleeF = dyn_cast<Function>(G->getGlobal())) { + const Type *CalleeRetTy = CalleeF->getReturnType(); + return CallerRetTy == CalleeRetTy; + } + return false; } FastISel * diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 0b906e657f9..193ef054c99 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -627,7 +627,7 @@ namespace llvm { /// IsEligibleForTailCallOptimization - Check whether the call is eligible /// for tail call optimization. Targets which want to do tail call /// optimization should implement this function. - bool IsEligibleForTailCallOptimization(SDValue Callee, const Type *RetTy, + bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, @@ -707,7 +707,7 @@ namespace llvm { DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp index e1e73a415f9..bf8c38fbddb 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -609,7 +609,7 @@ SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { /// XCore call implementation SDValue -XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, +XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.h b/llvm/lib/Target/XCore/XCoreISelLowering.h index c0b707d81b0..f7b620e5fba 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.h +++ b/llvm/lib/Target/XCore/XCoreISelLowering.h @@ -147,7 +147,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, |
