diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 48 |
1 files changed, 16 insertions, 32 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index cdeefb572ec..3c62d16d42e 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -210,7 +210,7 @@ multiclass AVX512_maskable_custom<bits<8> O, Format F, Pattern, itin>; // Prefer over VMOV*rrk Pat<> - let AddedComplexity = 20, isCommutable = IsKCommutable in + let isCommutable = IsKCommutable in def NAME#k: AVX512<O, F, Outs, MaskingIns, OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"# "$dst {${mask}}, "#IntelSrcAsm#"}", @@ -222,7 +222,7 @@ multiclass AVX512_maskable_custom<bits<8> O, Format F, // Zero mask does not add any restrictions to commute operands transformation. // So, it is Ok to use IsCommutable instead of IsKCommutable. - let AddedComplexity = 30, isCommutable = IsCommutable in // Prefer over VMOV*rrkz Pat<> + let isCommutable = IsCommutable in // Prefer over VMOV*rrkz Pat<> def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns, OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"# "$dst {${mask}} {z}, "#IntelSrcAsm#"}", @@ -883,7 +883,6 @@ multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr, (SrcInfo.VT (scalar_to_vector (SrcInfo.ScalarLdFrag addr:$src))))), (!cast<Instruction>(NAME#DestInfo.ZSuffix#m) addr:$src)>; - let AddedComplexity = 20 in def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask, (X86VBroadcast (SrcInfo.VT (scalar_to_vector @@ -891,7 +890,6 @@ multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr, DestInfo.RC:$src0)), (!cast<Instruction>(NAME#DestInfo.ZSuffix#mk) DestInfo.RC:$src0, DestInfo.KRCWM:$mask, addr:$src)>; - let AddedComplexity = 30 in def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask, (X86VBroadcast (SrcInfo.VT (scalar_to_vector @@ -2001,22 +1999,20 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode, [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode (_.VT _.RC:$src1), (i32 imm:$src2))))], NoItinerary>, EVEX_K; - let AddedComplexity = 20 in { - def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst), - (ins _.MemOp:$src1, i32u8imm:$src2), - OpcodeStr##_.Suffix## - "\t{$src2, $src1, $dst|$dst, $src1, $src2}", - [(set _.KRC:$dst, - (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))), - (i32 imm:$src2)))], NoItinerary>; - def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst), - (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2), - OpcodeStr##_.Suffix## - "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}", - [(set _.KRC:$dst,(or _.KRCWM:$mask, + def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst), + (ins _.MemOp:$src1, i32u8imm:$src2), + OpcodeStr##_.Suffix## + "\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.KRC:$dst, (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))), - (i32 imm:$src2))))], NoItinerary>, EVEX_K; - } + (i32 imm:$src2)))], NoItinerary>; + def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst), + (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2), + OpcodeStr##_.Suffix## + "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}", + [(set _.KRC:$dst,(or _.KRCWM:$mask, + (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))), + (i32 imm:$src2))))], NoItinerary>, EVEX_K; } } @@ -4920,7 +4916,6 @@ multiclass avx512_var_shift_int_lowering<string InstrStr, X86VectorVTInfo _, def : Pat<(_.VT (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2)))), (!cast<Instruction>(InstrStr#_.ZSuffix##rm) _.RC:$src1, addr:$src2)>; - let AddedComplexity = 20 in { def : Pat<(_.VT (vselect _.KRCWM:$mask, (X86vsrav _.RC:$src1, _.RC:$src2), _.RC:$src0)), (!cast<Instruction>(InstrStr#_.ZSuffix#rrk) _.RC:$src0, @@ -4930,8 +4925,6 @@ multiclass avx512_var_shift_int_lowering<string InstrStr, X86VectorVTInfo _, _.RC:$src0)), (!cast<Instruction>(InstrStr#_.ZSuffix##rmk) _.RC:$src0, _.KRC:$mask, _.RC:$src1, addr:$src2)>; - } - let AddedComplexity = 30 in { def : Pat<(_.VT (vselect _.KRCWM:$mask, (X86vsrav _.RC:$src1, _.RC:$src2), _.ImmAllZerosV)), (!cast<Instruction>(InstrStr#_.ZSuffix#rrkz) _.KRC:$mask, @@ -4941,7 +4934,6 @@ multiclass avx512_var_shift_int_lowering<string InstrStr, X86VectorVTInfo _, _.ImmAllZerosV)), (!cast<Instruction>(InstrStr#_.ZSuffix##rmkz) _.KRC:$mask, _.RC:$src1, addr:$src2)>; - } } } @@ -4953,14 +4945,12 @@ multiclass avx512_var_shift_int_lowering_mb<string InstrStr, X86VectorVTInfo _, (X86VBroadcast (_.ScalarLdFrag addr:$src2)))), (!cast<Instruction>(InstrStr#_.ZSuffix##rmb) _.RC:$src1, addr:$src2)>; - let AddedComplexity = 20 in def : Pat<(_.VT (vselect _.KRCWM:$mask, (X86vsrav _.RC:$src1, (X86VBroadcast (_.ScalarLdFrag addr:$src2))), _.RC:$src0)), (!cast<Instruction>(InstrStr#_.ZSuffix##rmbk) _.RC:$src0, _.KRC:$mask, _.RC:$src1, addr:$src2)>; - let AddedComplexity = 30 in def : Pat<(_.VT (vselect _.KRCWM:$mask, (X86vsrav _.RC:$src1, (X86VBroadcast (_.ScalarLdFrag addr:$src2))), @@ -6824,7 +6814,7 @@ let Defs = [EFLAGS], Predicates = [HasAVX512] in { /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> { - let AddedComplexity = 20 , Predicates = [HasAVX512] in { + let Predicates = [HasAVX512] in { defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst), (ins _.RC:$src1, _.RC:$src2), OpcodeStr, "$src2, $src1", "$src1, $src2", @@ -8957,7 +8947,6 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode, }// Constraints = "$src1 = $dst" // Additional patterns for matching passthru operand in other positions. - let AddedComplexity = 20 in { def : Pat<(_.VT (vselect _.KRCWM:$mask, (OpNode _.RC:$src3, _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), _.RC:$src1)), @@ -8968,7 +8957,6 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode, _.RC:$src1)), (!cast<Instruction>(NAME#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask, _.RC:$src2, _.RC:$src3, (VPTERNLOG213_imm8 imm:$src4))>; - } // Additional patterns for matching loads in other positions. def : Pat<(_.VT (OpNode (bitconvert (_.LdFrag addr:$src3)), @@ -8983,7 +8971,6 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode, // Additional patterns for matching zero masking with loads in other // positions. - let AddedComplexity = 30 in { def : Pat<(_.VT (vselect _.KRCWM:$mask, (OpNode (bitconvert (_.LdFrag addr:$src3)), _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), @@ -8996,18 +8983,15 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode, _.ImmAllZerosV)), (!cast<Instruction>(NAME#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask, _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; - } // Additional patterns for matching masked loads with different // operand orders. - let AddedComplexity = 20 in { def : Pat<(_.VT (vselect _.KRCWM:$mask, (OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)), _.RC:$src2, (i8 imm:$src4)), _.RC:$src1)), (!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask, _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; - } } multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{ |
