diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/MC/MCAssembler.cpp | 18 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 8 |
2 files changed, 15 insertions, 11 deletions
diff --git a/llvm/lib/MC/MCAssembler.cpp b/llvm/lib/MC/MCAssembler.cpp index 0fbd77c7f12..0d114fb7314 100644 --- a/llvm/lib/MC/MCAssembler.cpp +++ b/llvm/lib/MC/MCAssembler.cpp @@ -248,14 +248,18 @@ bool MCAssembler::EvaluateFixup(const MCObjectWriter &Writer, if (IsResolved) IsResolved = Writer.IsFixupFullyResolved(*this, Target, IsPCRel, DF); + bool ShouldAlignPC = Emitter.getFixupKindInfo(Fixup.getKind()).Flags & + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits; + assert((ShouldAlignPC ? IsPCRel : true) && + "FKF_IsAlignedDownTo32Bits is only allowed on PC-relative fixups!"); + if (IsPCRel) { - bool ShouldAlignPC = Emitter.getFixupKindInfo( - Fixup.getKind()).Flags & MCFixupKindInfo::FKF_IsAligned; - // PC should be aligned to a 4-byte value. - if (ShouldAlignPC) - Value -= Layout.getFragmentOffset(DF) + (Fixup.getOffset() & ~0x3); - else - Value -= Layout.getFragmentOffset(DF) + Fixup.getOffset(); + uint32_t Offset = Fixup.getOffset(); + + // A number of ARM fixups in Thumb mode require that the effective PC + // address be determined as the 32-bit aligned version of the actual offset. + if (ShouldAlignPC) Offset &= 0x3; + Value -= Layout.getFragmentOffset(DF) + Offset; } // ARM fixups based from a thumb function address need to have the low diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index db68f359a2c..1efcae03a4f 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -51,15 +51,15 @@ public: // Name Offset (bits) Size (bits) Flags { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAligned}, + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAligned}, + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAligned}, + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAligned}, + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, { "fixup_arm_branch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, |
