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-rw-r--r--llvm/lib/CodeGen/MIRParser/MILexer.cpp1
-rw-r--r--llvm/lib/CodeGen/MIRParser/MILexer.h4
-rw-r--r--llvm/lib/CodeGen/MIRParser/MIParser.cpp7
-rw-r--r--llvm/lib/CodeGen/MachineOperand.cpp37
-rw-r--r--llvm/lib/CodeGen/MachineVerifier.cpp8
-rw-r--r--llvm/lib/CodeGen/RegAllocFast.cpp2
-rw-r--r--llvm/lib/CodeGen/VirtRegMap.cpp1
-rw-r--r--llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp17
-rw-r--r--llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp11
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp5
10 files changed, 81 insertions, 12 deletions
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
index ac696923794..fe6d075726e 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
@@ -208,6 +208,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
.Case("internal", MIToken::kw_internal)
.Case("early-clobber", MIToken::kw_early_clobber)
.Case("debug-use", MIToken::kw_debug_use)
+ .Case("renamable", MIToken::kw_renamable)
.Case("tied-def", MIToken::kw_tied_def)
.Case("frame-setup", MIToken::kw_frame_setup)
.Case("debug-location", MIToken::kw_debug_location)
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h
index 6894fe8b0ac..f7027bea181 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.h
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.h
@@ -60,6 +60,7 @@ struct MIToken {
kw_internal,
kw_early_clobber,
kw_debug_use,
+ kw_renamable,
kw_tied_def,
kw_frame_setup,
kw_debug_location,
@@ -166,7 +167,8 @@ public:
return Kind == kw_implicit || Kind == kw_implicit_define ||
Kind == kw_def || Kind == kw_dead || Kind == kw_killed ||
Kind == kw_undef || Kind == kw_internal ||
- Kind == kw_early_clobber || Kind == kw_debug_use;
+ Kind == kw_early_clobber || Kind == kw_debug_use ||
+ Kind == kw_renamable;
}
bool isMemoryOperandFlag() const {
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index de951e42c8f..6ec3fc864c6 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1060,6 +1060,9 @@ bool MIParser::parseRegisterFlag(unsigned &Flags) {
case MIToken::kw_debug_use:
Flags |= RegState::Debug;
break;
+ case MIToken::kw_renamable:
+ Flags |= RegState::Renamable;
+ break;
default:
llvm_unreachable("The current token should be a register flag");
}
@@ -1212,7 +1215,8 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
Reg, Flags & RegState::Define, Flags & RegState::Implicit,
Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef,
Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug,
- Flags & RegState::InternalRead);
+ Flags & RegState::InternalRead, Flags & RegState::Renamable);
+
return false;
}
@@ -1880,6 +1884,7 @@ bool MIParser::parseMachineOperand(MachineOperand &Dest,
case MIToken::kw_internal:
case MIToken::kw_early_clobber:
case MIToken::kw_debug_use:
+ case MIToken::kw_renamable:
case MIToken::underscore:
case MIToken::NamedRegister:
case MIToken::VirtualRegister:
diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 8bd6a7a965b..b618e605dca 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -90,6 +90,7 @@ void MachineOperand::setIsDef(bool Val) {
assert((!Val || !isDebug()) && "Marking a debug operation as def");
if (IsDef == Val)
return;
+ assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
// MRI may keep uses and defs in different list positions.
if (MachineFunction *MF = getMFIfAvailable(*this)) {
MachineRegisterInfo &MRI = MF->getRegInfo();
@@ -101,6 +102,34 @@ void MachineOperand::setIsDef(bool Val) {
IsDef = Val;
}
+bool MachineOperand::isRenamable() const {
+ assert(isReg() && "Wrong MachineOperand accessor");
+ assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
+ "isRenamable should only be checked on physical registers");
+ return IsRenamable;
+}
+
+void MachineOperand::setIsRenamable(bool Val) {
+ assert(isReg() && "Wrong MachineOperand accessor");
+ assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
+ "setIsRenamable should only be called on physical registers");
+ if (const MachineInstr *MI = getParent())
+ if ((isDef() && MI->hasExtraDefRegAllocReq()) ||
+ (isUse() && MI->hasExtraSrcRegAllocReq()))
+ assert(!Val && "isRenamable should be false for "
+ "hasExtraDefRegAllocReq/hasExtraSrcRegAllocReq opcodes");
+ IsRenamable = Val;
+}
+
+void MachineOperand::setIsRenamableIfNoExtraRegAllocReq() {
+ if (const MachineInstr *MI = getParent())
+ if ((isDef() && MI->hasExtraDefRegAllocReq()) ||
+ (isUse() && MI->hasExtraSrcRegAllocReq()))
+ return;
+
+ setIsRenamable(true);
+}
+
// If this operand is currently a register operand, and if this is in a
// function, deregister the operand from the register's use/def list.
void MachineOperand::removeRegFromUses() {
@@ -194,13 +223,15 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
RegInfo->removeRegOperandFromUseList(this);
// Change this to a register and set the reg#.
+ assert(!(isDead && !isDef) && "Dead flag on non-def");
+ assert(!(isKill && isDef) && "Kill flag on def");
OpKind = MO_Register;
SmallContents.RegNo = Reg;
SubReg_TargetFlags = 0;
IsDef = isDef;
IsImp = isImp;
- IsKill = isKill;
- IsDead = isDead;
+ IsDeadOrKill = isKill | isDead;
+ IsRenamable = false;
IsUndef = isUndef;
IsInternalRead = false;
IsEarlyClobber = false;
@@ -389,6 +420,8 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
OS << "early-clobber ";
if (isDebug())
OS << "debug-use ";
+ if (TargetRegisterInfo::isPhysicalRegister(getReg()) && isRenamable())
+ OS << "renamable ";
OS << printReg(Reg, TRI);
// Print the sub register.
if (unsigned SubReg = getSubReg()) {
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index d5658db161a..6ed6f0aced9 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1101,6 +1101,14 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
}
}
+ if (MO->isRenamable() &&
+ ((MO->isDef() && MI->hasExtraDefRegAllocReq()) ||
+ (MO->isUse() && MI->hasExtraSrcRegAllocReq()))) {
+ report("Illegal isRenamable setting for opcode with extra regalloc "
+ "requirements",
+ MO, MONum);
+ return;
+ }
} else {
// Virtual register.
const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index 97011d55d89..f6adb2509bf 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -699,11 +699,13 @@ bool RegAllocFast::setPhysReg(MachineInstr &MI, unsigned OpNum,
bool Dead = MO.isDead();
if (!MO.getSubReg()) {
MO.setReg(PhysReg);
+ MO.setIsRenamableIfNoExtraRegAllocReq();
return MO.isKill() || Dead;
}
// Handle subregister index.
MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
+ MO.setIsRenamableIfNoExtraRegAllocReq();
MO.setSubReg(0);
// A kill flag implies killing the full register. Add corresponding super
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 6e5674bb8bc..00a4eb7808f 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -530,6 +530,7 @@ void VirtRegRewriter::rewrite() {
// Rewrite. Note we could have used MachineOperand::substPhysReg(), but
// we need the inlining here.
MO.setReg(PhysReg);
+ MO.setIsRenamableIfNoExtraRegAllocReq();
}
// Add any missing super-register kills after rewriting the whole
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index b2f4a529efa..02bf7739e15 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1357,25 +1357,34 @@ void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
MachineInstrBuilder LDM, STM;
if (isThumb1 || !MI->getOperand(1).isDead()) {
+ MachineOperand LDWb(MI->getOperand(1));
+ LDWb.setIsRenamable(false);
LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
: isThumb1 ? ARM::tLDMIA_UPD
: ARM::LDMIA_UPD))
- .add(MI->getOperand(1));
+ .add(LDWb);
} else {
LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
}
if (isThumb1 || !MI->getOperand(0).isDead()) {
+ MachineOperand STWb(MI->getOperand(0));
+ STWb.setIsRenamable(false);
STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
: isThumb1 ? ARM::tSTMIA_UPD
: ARM::STMIA_UPD))
- .add(MI->getOperand(0));
+ .add(STWb);
} else {
STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
}
- LDM.add(MI->getOperand(3)).add(predOps(ARMCC::AL));
- STM.add(MI->getOperand(2)).add(predOps(ARMCC::AL));
+ MachineOperand LDBase(MI->getOperand(3));
+ LDBase.setIsRenamable(false);
+ LDM.add(LDBase).add(predOps(ARMCC::AL));
+
+ MachineOperand STBase(MI->getOperand(2));
+ STBase.setIsRenamable(false);
+ STM.add(STBase).add(predOps(ARMCC::AL));
// Sort the scratch registers into ascending order.
const TargetRegisterInfo &TRI = getRegisterInfo();
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index eab84ae59e2..1c64e3d1a1c 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -606,8 +606,11 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
// Transfer the destination register operand.
MIB.add(MI.getOperand(OpIdx++));
- if (IsExt)
- MIB.add(MI.getOperand(OpIdx++));
+ if (IsExt) {
+ MachineOperand VdSrc(MI.getOperand(OpIdx++));
+ VdSrc.setIsRenamable(false);
+ MIB.add(VdSrc);
+ }
bool SrcIsKill = MI.getOperand(OpIdx).isKill();
unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
@@ -616,7 +619,9 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
MIB.addReg(D0);
// Copy the other source register operand.
- MIB.add(MI.getOperand(OpIdx++));
+ MachineOperand VmSrc(MI.getOperand(OpIdx++));
+ VmSrc.setIsRenamable(false);
+ MIB.add(VmSrc);
// Copy the predicate operands.
MIB.add(MI.getOperand(OpIdx++));
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 0a0869afb86..e4296a77c0d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -8974,8 +8974,11 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
// Thumb1 post-indexed loads are really just single-register LDMs.
case ARM::tLDR_postidx: {
+ MachineOperand Def(MI.getOperand(1));
+ if (TargetRegisterInfo::isPhysicalRegister(Def.getReg()))
+ Def.setIsRenamable(false);
BuildMI(*BB, MI, dl, TII->get(ARM::tLDMIA_UPD))
- .add(MI.getOperand(1)) // Rn_wb
+ .add(Def) // Rn_wb
.add(MI.getOperand(2)) // Rn
.add(MI.getOperand(3)) // PredImm
.add(MI.getOperand(4)) // PredReg
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