diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFeatures.h | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 |
2 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMFeatures.h b/llvm/lib/Target/ARM/ARMFeatures.h index dafc4b3a82b..2580f7bf7f4 100644 --- a/llvm/lib/Target/ARM/ARMFeatures.h +++ b/llvm/lib/Target/ARM/ARMFeatures.h @@ -19,7 +19,7 @@ namespace llvm { template<typename InstrType> // could be MachineInstr or MCInst -inline bool isV8EligibleForIT(InstrType *Instr, int BLXOperandIndex = 0) { +inline bool isV8EligibleForIT(InstrType *Instr) { switch (Instr->getOpcode()) { default: return false; @@ -70,14 +70,13 @@ inline bool isV8EligibleForIT(InstrType *Instr, int BLXOperandIndex = 0) { return true; // there are some "conditionally deprecated" opcodes case ARM::tADDspr: + case ARM::tBLXr: return Instr->getOperand(2).getReg() != ARM::PC; // ADD PC, SP and BLX PC were always unpredictable, // now on top of it they're deprecated case ARM::tADDrSP: case ARM::tBX: return Instr->getOperand(0).getReg() != ARM::PC; - case ARM::tBLXr: - return Instr->getOperand(BLXOperandIndex).getReg() != ARM::PC; case ARM::tADDhirr: return Instr->getOperand(0).getReg() != ARM::PC && Instr->getOperand(2).getReg() != ARM::PC; diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index dc9a308bb95..216f4aa2d64 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -7956,7 +7956,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, // Only after the instruction is fully processed, we can validate it if (wasInITBlock && hasV8Ops() && isThumb() && - !isV8EligibleForIT(&Inst, 2)) { + !isV8EligibleForIT(&Inst)) { Warning(IDLoc, "deprecated instruction in IT block"); } } |
