summaryrefslogtreecommitdiffstats
path: root/llvm/lib
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp20
-rw-r--r--llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp5
-rw-r--r--llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp40
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp19
-rw-r--r--llvm/lib/Target/ARM/ARMLegalizerInfo.cpp12
-rw-r--r--llvm/lib/Target/Mips/MipsLegalizerInfo.cpp12
6 files changed, 57 insertions, 51 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp b/llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp
index 07e0cb662b5..601d50e9806 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp
@@ -38,15 +38,19 @@ LegalityPredicate LegalityPredicates::typePairInSet(
};
}
-LegalityPredicate LegalityPredicates::typePairAndMemSizeInSet(
+LegalityPredicate LegalityPredicates::typePairAndMemDescInSet(
unsigned TypeIdx0, unsigned TypeIdx1, unsigned MMOIdx,
- std::initializer_list<TypePairAndMemSize> TypesAndMemSizeInit) {
- SmallVector<TypePairAndMemSize, 4> TypesAndMemSize = TypesAndMemSizeInit;
- return [=](const LegalityQuery &Query) {
- TypePairAndMemSize Match = {Query.Types[TypeIdx0], Query.Types[TypeIdx1],
- Query.MMODescrs[MMOIdx].SizeInBits};
- return std::find(TypesAndMemSize.begin(), TypesAndMemSize.end(), Match) !=
- TypesAndMemSize.end();
+ std::initializer_list<TypePairAndMemDesc> TypesAndMemDescInit) {
+ SmallVector<TypePairAndMemDesc, 4> TypesAndMemDesc = TypesAndMemDescInit;
+ return [=](const LegalityQuery &Query) {
+ TypePairAndMemDesc Match = {Query.Types[TypeIdx0], Query.Types[TypeIdx1],
+ Query.MMODescrs[MMOIdx].SizeInBits,
+ Query.MMODescrs[MMOIdx].AlignInBits};
+ return std::find_if(
+ TypesAndMemDesc.begin(), TypesAndMemDesc.end(),
+ [=](const TypePairAndMemDesc &Entry) ->bool {
+ return Match.isCompatible(Entry);
+ }) != TypesAndMemDesc.end();
};
}
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
index f2fc2e78a9e..e17993987f0 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
@@ -423,8 +423,9 @@ LegalizerInfo::getAction(const MachineInstr &MI,
SmallVector<LegalityQuery::MemDesc, 2> MemDescrs;
for (const auto &MMO : MI.memoperands())
- MemDescrs.push_back(
- {MMO->getSize() /* in bytes */ * 8, MMO->getOrdering()});
+ MemDescrs.push_back({8 * MMO->getSize() /* in bits */,
+ 8 * MMO->getAlignment(),
+ MMO->getOrdering()});
return getAction({MI.getOpcode(), Types, MemDescrs});
}
diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
index 34ce38896da..3c57af84f03 100644
--- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -192,12 +192,12 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
.widenScalarToNextPow2(0);
getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
- .legalForTypesWithMemSize({{s32, p0, 8},
- {s32, p0, 16},
- {s32, p0, 32},
- {s64, p0, 64},
- {p0, p0, 64},
- {v2s32, p0, 64}})
+ .legalForTypesWithMemDesc({{s32, p0, 8, 8},
+ {s32, p0, 16, 8},
+ {s32, p0, 32, 8},
+ {s64, p0, 64, 8},
+ {p0, p0, 64, 8},
+ {v2s32, p0, 64, 8}})
.clampScalar(0, s32, s64)
.widenScalarToNextPow2(0)
// TODO: We could support sum-of-pow2's but the lowering code doesn't know
@@ -207,15 +207,15 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
.lower();
getActionDefinitionsBuilder(G_LOAD)
- .legalForTypesWithMemSize({{s8, p0, 8},
- {s16, p0, 16},
- {s32, p0, 32},
- {s64, p0, 64},
- {p0, p0, 64},
- {v2s32, p0, 64}})
+ .legalForTypesWithMemDesc({{s8, p0, 8, 8},
+ {s16, p0, 16, 8},
+ {s32, p0, 32, 8},
+ {s64, p0, 64, 8},
+ {p0, p0, 64, 8},
+ {v2s32, p0, 64, 8}})
// These extends are also legal
- .legalForTypesWithMemSize({{s32, p0, 8},
- {s32, p0, 16}})
+ .legalForTypesWithMemDesc({{s32, p0, 8, 8},
+ {s32, p0, 16, 8}})
.clampScalar(0, s8, s64)
.widenScalarToNextPow2(0)
// TODO: We could support sum-of-pow2's but the lowering code doesn't know
@@ -229,12 +229,12 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
.clampMaxNumElements(0, s64, 1);
getActionDefinitionsBuilder(G_STORE)
- .legalForTypesWithMemSize({{s8, p0, 8},
- {s16, p0, 16},
- {s32, p0, 32},
- {s64, p0, 64},
- {p0, p0, 64},
- {v2s32, p0, 64}})
+ .legalForTypesWithMemDesc({{s8, p0, 8, 8},
+ {s16, p0, 16, 8},
+ {s32, p0, 32, 8},
+ {s64, p0, 64, 8},
+ {p0, p0, 64, 8},
+ {v2s32, p0, 64, 8}})
.clampScalar(0, s8, s64)
.widenScalarToNextPow2(0)
// TODO: We could support sum-of-pow2's but the lowering code doesn't know
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index c68190baf6f..4487bffacdc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -397,17 +397,18 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
.clampScalar(0, S32, S64);
+ // FIXME: Handle alignment requirements.
auto &ExtLoads = getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
- .legalForTypesWithMemSize({
- {S32, GlobalPtr, 8},
- {S32, GlobalPtr, 16},
- {S32, LocalPtr, 8},
- {S32, LocalPtr, 16},
- {S32, PrivatePtr, 8},
- {S32, PrivatePtr, 16}});
+ .legalForTypesWithMemDesc({
+ {S32, GlobalPtr, 8, 8},
+ {S32, GlobalPtr, 16, 8},
+ {S32, LocalPtr, 8, 8},
+ {S32, LocalPtr, 16, 8},
+ {S32, PrivatePtr, 8, 8},
+ {S32, PrivatePtr, 16, 8}});
if (ST.hasFlatAddressSpace()) {
- ExtLoads.legalForTypesWithMemSize({{S32, FlatPtr, 8},
- {S32, FlatPtr, 16}});
+ ExtLoads.legalForTypesWithMemDesc({{S32, FlatPtr, 8, 8},
+ {S32, FlatPtr, 16, 8}});
}
ExtLoads.clampScalar(0, S32, S32)
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index 10320e59897..2b217ce660e 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -131,12 +131,12 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
// floating point to them.
auto &LoadStoreBuilder =
getActionDefinitionsBuilder({G_LOAD, G_STORE})
- .legalForTypesWithMemSize({
- {s1, p0, 8},
- {s8, p0, 8},
- {s16, p0, 16},
- {s32, p0, 32},
- {p0, p0, 32}});
+ .legalForTypesWithMemDesc({
+ {s1, p0, 8, 8},
+ {s8, p0, 8, 8},
+ {s16, p0, 16, 8},
+ {s32, p0, 32, 8},
+ {p0, p0, 32, 8}});
getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}});
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index 7003f5395ee..4fddabcedfe 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -36,15 +36,15 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
.lowerFor({{s32, s1}});
getActionDefinitionsBuilder({G_LOAD, G_STORE})
- .legalForTypesWithMemSize({{s32, p0, 8},
- {s32, p0, 16},
- {s32, p0, 32},
- {p0, p0, 32}})
+ .legalForTypesWithMemDesc({{s32, p0, 8, 8},
+ {s32, p0, 16, 8},
+ {s32, p0, 32, 8},
+ {p0, p0, 32, 8}})
.minScalar(0, s32);
getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
- .legalForTypesWithMemSize({{s32, p0, 8},
- {s32, p0, 16}})
+ .legalForTypesWithMemDesc({{s32, p0, 8, 8},
+ {s32, p0, 16, 8}})
.minScalar(0, s32);
getActionDefinitionsBuilder(G_SELECT)
OpenPOWER on IntegriCloud