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-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLowering.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 6ba9a31b316..218f5c3e554 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2987,9 +2987,10 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(
switch (VT.SimpleTy) {
default:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
- case MVT::i32:
- case MVT::i16:
+ case MVT::i1:
case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
case MVT::f32:
return std::make_pair(0U, &Hexagon::IntRegsRegClass);
case MVT::i64:
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