diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 462 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp | 24 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.td | 485 |
4 files changed, 365 insertions, 622 deletions
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 88c252034fe..6ffb062edd4 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -61,15 +61,18 @@ public: enum ImmTy { ImmTyNone, - ImmTyDSOffset0, - ImmTyDSOffset1, ImmTyGDS, + ImmTyOffen, + ImmTyIdxen, + ImmTyAddr64, ImmTyOffset, + ImmTyOffset0, + ImmTyOffset1, ImmTyGLC, ImmTySLC, ImmTyTFE, - ImmTyClamp, - ImmTyOMod, + ImmTyClampSI, + ImmTyOModSI, ImmTyDppCtrl, ImmTyDppRowMask, ImmTyDppBankMask, @@ -149,13 +152,6 @@ public: } } - bool defaultTokenHasSuffix() const { - StringRef Token(Tok.Data, Tok.Length); - - return Token.endswith("_e32") || Token.endswith("_e64") || - Token.endswith("_dpp"); - } - bool isToken() const override { return Kind == Token; } @@ -178,16 +174,6 @@ public: F == 2.0 || F == -2.0 || F == 4.0 || F == -4.0); } - bool isDSOffset0() const { - assert(isImm()); - return Imm.Type == ImmTyDSOffset0; - } - - bool isDSOffset1() const { - assert(isImm()); - return Imm.Type == ImmTyDSOffset1; - } - int64_t getImm() const { return Imm.Val; } @@ -213,12 +199,12 @@ public: return isImm() && Imm.Type == ImmT; } - bool isClamp() const { - return isImmTy(ImmTyClamp); + bool isClampSI() const { + return isImmTy(ImmTyClampSI); } - bool isOMod() const { - return isImmTy(ImmTyOMod); + bool isOModSI() const { + return isImmTy(ImmTyOModSI); } bool isImmModifier() const { @@ -235,9 +221,15 @@ public: bool isLWE() const { return isImmTy(ImmTyLWE); } bool isMod() const { - return isClamp() || isOMod(); + return isClampSI() || isOModSI(); } + bool isOffen() const { return isImmTy(ImmTyOffen); } + bool isIdxen() const { return isImmTy(ImmTyIdxen); } + bool isAddr64() const { return isImmTy(ImmTyAddr64); } + bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); } + bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<16>(getImm()); } + bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); } bool isGDS() const { return isImmTy(ImmTyGDS); } bool isGLC() const { return isImmTy(ImmTyGLC); } bool isSLC() const { return isImmTy(ImmTySLC); } @@ -347,16 +339,47 @@ public: return EndLoc; } + void printImmTy(raw_ostream& OS, ImmTy Type) const { + switch (Type) { + case ImmTyNone: OS << "None"; break; + case ImmTyGDS: OS << "GDS"; break; + case ImmTyOffen: OS << "Offen"; break; + case ImmTyIdxen: OS << "Idxen"; break; + case ImmTyAddr64: OS << "Addr64"; break; + case ImmTyOffset: OS << "Offset"; break; + case ImmTyOffset0: OS << "Offset0"; break; + case ImmTyOffset1: OS << "Offset1"; break; + case ImmTyGLC: OS << "GLC"; break; + case ImmTySLC: OS << "SLC"; break; + case ImmTyTFE: OS << "TFE"; break; + case ImmTyClampSI: OS << "ClampSI"; break; + case ImmTyOModSI: OS << "OModSI"; break; + case ImmTyDppCtrl: OS << "DppCtrl"; break; + case ImmTyDppRowMask: OS << "DppRowMask"; break; + case ImmTyDppBankMask: OS << "DppBankMask"; break; + case ImmTyDppBoundCtrl: OS << "DppBoundCtrl"; break; + case ImmTySdwaSel: OS << "SdwaSel"; break; + case ImmTySdwaDstUnused: OS << "SdwaDstUnused"; break; + case ImmTyDMask: OS << "DMask"; break; + case ImmTyUNorm: OS << "UNorm"; break; + case ImmTyDA: OS << "DA"; break; + case ImmTyR128: OS << "R128"; break; + case ImmTyLWE: OS << "LWE"; break; + case ImmTyHwreg: OS << "Hwreg"; break; + } + } + void print(raw_ostream &OS) const override { switch (Kind) { case Register: OS << "<register " << getReg() << " mods: " << Reg.Modifiers << '>'; break; case Immediate: - if (Imm.Type != AMDGPUOperand::ImmTyNone) - OS << getImm(); - else - OS << '<' << getImm() << " mods: " << Imm.Modifiers << '>'; + OS << '<' << getImm(); + if (getImmTy() != ImmTyNone) { + OS << " type: "; printImmTy(OS, getImmTy()); + } + OS << " mods: " << Imm.Modifiers << '>'; break; case Token: OS << '\'' << getToken() << '\''; @@ -414,8 +437,6 @@ public: return Op; } - bool isDSOffset() const; - bool isDSOffset01() const; bool isSWaitCnt() const; bool isHwreg() const; bool isMubufOffset() const; @@ -521,43 +542,55 @@ public: SMLoc NameLoc, OperandVector &Operands) override; OperandMatchResultTy parseIntWithPrefix(const char *Prefix, int64_t &Int, - int64_t Default = 0); + int64_t Default = 0, bool AddDefault = false); OperandMatchResultTy parseIntWithPrefix(const char *Prefix, OperandVector &Operands, - enum AMDGPUOperand::ImmTy ImmTy = - AMDGPUOperand::ImmTyNone); + enum AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone, + int64_t Default = 0, bool AddDefault = false, + bool (*ConvertResult)(int64_t&) = 0); OperandMatchResultTy parseNamedBit(const char *Name, OperandVector &Operands, enum AMDGPUOperand::ImmTy ImmTy = - AMDGPUOperand::ImmTyNone); + AMDGPUOperand::ImmTyNone, + bool AddDefault = false); OperandMatchResultTy parseOptionalOps( const ArrayRef<OptionalOperand> &OptionalOps, OperandVector &Operands); OperandMatchResultTy parseStringWithPrefix(const char *Prefix, StringRef &Value); + OperandMatchResultTy parseOptionalOperand(OperandVector &Operands, const OptionalOperand& Op, bool AddDefault); + OperandMatchResultTy parseAMDGPUOperand(OperandVector &Operands, StringRef Name); void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands); void cvtDS(MCInst &Inst, const OperandVector &Operands); - OperandMatchResultTy parseDSOptionalOps(OperandVector &Operands); - OperandMatchResultTy parseDSOff01OptionalOps(OperandVector &Operands); - OperandMatchResultTy parseDSOffsetOptional(OperandVector &Operands); bool parseCnt(int64_t &IntVal); OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands); - bool parseHwreg(int64_t &HwRegCode, int64_t &Offset, int64_t &Width, bool &IsIdentifier); - OperandMatchResultTy parseHwregOp(OperandVector &Operands); + bool parseHwregOperand(int64_t &HwRegCode, int64_t &Offset, int64_t &Width, bool &IsIdentifier); + OperandMatchResultTy parseHwreg(OperandVector &Operands); OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands); - OperandMatchResultTy parseFlatOptionalOps(OperandVector &Operands); - OperandMatchResultTy parseFlatAtomicOptionalOps(OperandVector &Operands); void cvtFlat(MCInst &Inst, const OperandVector &Operands); void cvtFlatAtomic(MCInst &Inst, const OperandVector &Operands); void cvtMubuf(MCInst &Inst, const OperandVector &Operands); - OperandMatchResultTy parseOffset(OperandVector &Operands); - OperandMatchResultTy parseMubufOptionalOps(OperandVector &Operands); - OperandMatchResultTy parseGLC(OperandVector &Operands); - OperandMatchResultTy parseSLC(OperandVector &Operands); - OperandMatchResultTy parseTFE(OperandVector &Operands); + OperandMatchResultTy parseOModSI(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "omod"); } + OperandMatchResultTy parseClampSI(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "clamp"); } + OperandMatchResultTy parseSMRDOffset(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "smrd_offset"); } + OperandMatchResultTy parseSMRDLiteralOffset(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "smrd_literal_offset"); } + OperandMatchResultTy parseDPPCtrl(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "dpp_ctrl"); } + OperandMatchResultTy parseRowMask(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "row_mask"); } + OperandMatchResultTy parseBankMask(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "bank_mask"); } + OperandMatchResultTy parseBoundCtrl(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "bound_ctrl"); } + OperandMatchResultTy parseOffen(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "offen"); } + OperandMatchResultTy parseIdxen(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "idxen"); } + OperandMatchResultTy parseAddr64(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "addr64"); } + OperandMatchResultTy parseOffset(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "offset"); } + OperandMatchResultTy parseOffset0(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "offset0"); } + OperandMatchResultTy parseOffset1(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "offset1"); } + OperandMatchResultTy parseGLC(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "glc"); } + OperandMatchResultTy parseSLC(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "slc"); } + OperandMatchResultTy parseTFE(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "tfe"); } + OperandMatchResultTy parseGDS(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "gds"); } OperandMatchResultTy parseDMask(OperandVector &Operands); OperandMatchResultTy parseUNorm(OperandVector &Operands); @@ -565,6 +598,8 @@ public: OperandMatchResultTy parseR128(OperandVector &Operands); OperandMatchResultTy parseLWE(OperandVector &Operands); + OperandMatchResultTy parseOModOperand(OperandVector &Operands); + void cvtId(MCInst &Inst, const OperandVector &Operands); void cvtVOP3_2_mod(MCInst &Inst, const OperandVector &Operands); void cvtVOP3_2_nomod(MCInst &Inst, const OperandVector &Operands); @@ -573,10 +608,8 @@ public: void cvtMIMG(MCInst &Inst, const OperandVector &Operands); void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands); - OperandMatchResultTy parseVOP3OptionalOps(OperandVector &Operands); - OperandMatchResultTy parseDPPCtrlOps(OperandVector &Operands); - OperandMatchResultTy parseDPPOptionalOps(OperandVector &Operands); + OperandMatchResultTy parseDPPCtrlOps(OperandVector &Operands, bool AddDefault); void cvtDPP_mod(MCInst &Inst, const OperandVector &Operands); void cvtDPP_nomod(MCInst &Inst, const OperandVector &Operands); void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool HasMods); @@ -1109,8 +1142,8 @@ static bool operandsHaveModifiers(const OperandVector &Operands) { return true; if (Op.isImm() && Op.hasModifiers()) return true; - if (Op.isImm() && (Op.getImmTy() == AMDGPUOperand::ImmTyOMod || - Op.getImmTy() == AMDGPUOperand::ImmTyClamp)) + if (Op.isImm() && (Op.getImmTy() == AMDGPUOperand::ImmTyOModSI || + Op.getImmTy() == AMDGPUOperand::ImmTyClampSI)) return true; } return false; @@ -1213,12 +1246,19 @@ AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { } Operands.push_back(std::move(R)); } else { - ResTy = parseVOP3OptionalOps(Operands); if (ResTy == MatchOperand_NoMatch) { const auto &Tok = Parser.getTok(); Operands.push_back(AMDGPUOperand::CreateToken(Tok.getString(), Tok.getLoc())); Parser.Lex(); + if (getLexer().is(AsmToken::Colon)) { + Parser.Lex(); + if (getLexer().is(AsmToken::Identifier)) { + Parser.Lex(); + } + } + } else { + return ResTy; } } return MatchOperand_Success; @@ -1243,6 +1283,10 @@ bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info, // Add the instruction mnemonic Operands.push_back(AMDGPUOperand::CreateToken(Name, NameLoc)); + + if (Name.endswith("_e64")) { Name = Name.substr(0, Name.size() - 4); } + if (Name.endswith("_e32")) { Name = Name.substr(0, Name.size() - 4); } + while (!getLexer().is(AsmToken::EndOfStatement)) { AMDGPUAsmParser::OperandMatchResultTy Res = parseOperand(Operands, Name); @@ -1268,7 +1312,7 @@ bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info, AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &Int, - int64_t Default) { + int64_t Default, bool AddDefault) { // We are at the end of the statement, and this is a default argument, so // use a default value. if (getLexer().is(AsmToken::EndOfStatement)) { @@ -1279,9 +1323,14 @@ AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &Int, switch(getLexer().getKind()) { default: return MatchOperand_NoMatch; case AsmToken::Identifier: { - StringRef OffsetName = Parser.getTok().getString(); - if (!OffsetName.equals(Prefix)) + StringRef Name = Parser.getTok().getString(); + if (!Name.equals(Prefix)) { + if (AddDefault) { + Int = Default; + return MatchOperand_Success; + } return MatchOperand_NoMatch; + } Parser.Lex(); if (getLexer().isNot(AsmToken::Colon)) @@ -1301,22 +1350,29 @@ AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &Int, AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands, - enum AMDGPUOperand::ImmTy ImmTy) { + enum AMDGPUOperand::ImmTy ImmTy, + int64_t Default, bool AddDefault, + bool (*ConvertResult)(int64_t&)) { SMLoc S = Parser.getTok().getLoc(); - int64_t Offset = 0; + int64_t Value = 0; - AMDGPUAsmParser::OperandMatchResultTy Res = parseIntWithPrefix(Prefix, Offset); + AMDGPUAsmParser::OperandMatchResultTy Res = parseIntWithPrefix(Prefix, Value, Default, AddDefault); if (Res != MatchOperand_Success) return Res; - Operands.push_back(AMDGPUOperand::CreateImm(Offset, S, ImmTy)); + if (ConvertResult && !ConvertResult(Value)) { + return MatchOperand_ParseFail; + } + + Operands.push_back(AMDGPUOperand::CreateImm(Value, S, ImmTy)); return MatchOperand_Success; } AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands, - enum AMDGPUOperand::ImmTy ImmTy) { + enum AMDGPUOperand::ImmTy ImmTy, + bool AddDefault) { int64_t Bit = 0; SMLoc S = Parser.getTok().getLoc(); @@ -1333,7 +1389,11 @@ AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands, Bit = 0; Parser.Lex(); } else { - return MatchOperand_NoMatch; + if (AddDefault) { + Bit = 0; + } else { + return MatchOperand_NoMatch; + } } break; } @@ -1438,47 +1498,6 @@ AMDGPUAsmParser::parseStringWithPrefix(const char *Prefix, StringRef &Value) { // ds //===----------------------------------------------------------------------===// -static const OptionalOperand DSOptionalOps [] = { - {"offset", AMDGPUOperand::ImmTyOffset, false, 0, nullptr}, - {"gds", AMDGPUOperand::ImmTyGDS, true, 0, nullptr} -}; - -static const OptionalOperand DSOptionalOpsOff01 [] = { - {"offset0", AMDGPUOperand::ImmTyDSOffset0, false, 0, nullptr}, - {"offset1", AMDGPUOperand::ImmTyDSOffset1, false, 0, nullptr}, - {"gds", AMDGPUOperand::ImmTyGDS, true, 0, nullptr} -}; - -AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseDSOptionalOps(OperandVector &Operands) { - return parseOptionalOps(DSOptionalOps, Operands); -} -AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseDSOff01OptionalOps(OperandVector &Operands) { - return parseOptionalOps(DSOptionalOpsOff01, Operands); -} - -AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseDSOffsetOptional(OperandVector &Operands) { - SMLoc S = Parser.getTok().getLoc(); - AMDGPUAsmParser::OperandMatchResultTy Res = - parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset); - if (Res == MatchOperand_NoMatch) { - Operands.push_back(AMDGPUOperand::CreateImm(0, S, - AMDGPUOperand::ImmTyOffset)); - Res = MatchOperand_Success; - } - return Res; -} - -bool AMDGPUOperand::isDSOffset() const { - return isImm() && isUInt<16>(getImm()); -} - -bool AMDGPUOperand::isDSOffset01() const { - return isImm() && isUInt<8>(getImm()); -} - void AMDGPUAsmParser::cvtDSOffset01(MCInst &Inst, const OperandVector &Operands) { @@ -1497,8 +1516,8 @@ void AMDGPUAsmParser::cvtDSOffset01(MCInst &Inst, OptionalIdx[Op.getImmTy()] = i; } - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDSOffset0); - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDSOffset1); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset0); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset1); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS); Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0 @@ -1612,7 +1631,7 @@ AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) { return MatchOperand_Success; } -bool AMDGPUAsmParser::parseHwreg(int64_t &HwRegCode, int64_t &Offset, int64_t &Width, bool &IsIdentifier) { +bool AMDGPUAsmParser::parseHwregOperand(int64_t &HwRegCode, int64_t &Offset, int64_t &Width, bool &IsIdentifier) { if (Parser.getTok().getString() != "hwreg") return true; Parser.Lex(); @@ -1673,7 +1692,7 @@ bool AMDGPUAsmParser::parseHwreg(int64_t &HwRegCode, int64_t &Offset, int64_t &W } AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseHwregOp(OperandVector &Operands) { +AMDGPUAsmParser::parseHwreg(OperandVector &Operands) { int64_t Imm16Val = 0; SMLoc S = Parser.getTok().getLoc(); @@ -1695,7 +1714,7 @@ AMDGPUAsmParser::parseHwregOp(OperandVector &Operands) { int64_t HwRegCode = -1; int64_t Offset = 0; // default int64_t Width = 32; // default - if (parseHwreg(HwRegCode, Offset, Width, IsIdentifier)) + if (parseHwregOperand(HwRegCode, Offset, Width, IsIdentifier)) return MatchOperand_ParseFail; // HwRegCode (6) [5:0] // Offset (5) [10:6] @@ -1757,27 +1776,6 @@ AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) { // flat //===----------------------------------------------------------------------===// -static const OptionalOperand FlatOptionalOps [] = { - {"glc", AMDGPUOperand::ImmTyGLC, true, 0, nullptr}, - {"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr}, - {"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr} -}; - -static const OptionalOperand FlatAtomicOptionalOps [] = { - {"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr}, - {"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr} -}; - -AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseFlatOptionalOps(OperandVector &Operands) { - return parseOptionalOps(FlatOptionalOps, Operands); -} - -AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseFlatAtomicOptionalOps(OperandVector &Operands) { - return parseOptionalOps(FlatAtomicOptionalOps, Operands); -} - void AMDGPUAsmParser::cvtFlat(MCInst &Inst, const OperandVector &Operands) { OptionalImmIndexMap OptionalIdx; @@ -1828,38 +1826,6 @@ void AMDGPUAsmParser::cvtFlatAtomic(MCInst &Inst, // mubuf //===----------------------------------------------------------------------===// -static const OptionalOperand MubufOptionalOps [] = { - {"offset", AMDGPUOperand::ImmTyOffset, false, 0, nullptr}, - {"glc", AMDGPUOperand::ImmTyGLC, true, 0, nullptr}, - {"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr}, - {"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr} -}; - -AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseMubufOptionalOps(OperandVector &Operands) { - return parseOptionalOps(MubufOptionalOps, Operands); -} - -AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseOffset(OperandVector &Operands) { - return parseIntWithPrefix("offset", Operands); -} - -AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseGLC(OperandVector &Operands) { - return parseNamedBit("glc", Operands); -} - -AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseSLC(OperandVector &Operands) { - return parseNamedBit("slc", Operands); -} - -AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseTFE(OperandVector &Operands) { - return parseNamedBit("tfe", Operands); -} - bool AMDGPUOperand::isMubufOffset() const { return isImmTy(ImmTyOffset) && isUInt<12>(getImm()); } @@ -1972,64 +1938,103 @@ static bool ConvertOmodDiv(int64_t &Div) { return false; } -static const OptionalOperand VOP3OptionalOps [] = { - {"clamp", AMDGPUOperand::ImmTyClamp, true, 0, nullptr}, - {"mul", AMDGPUOperand::ImmTyOMod, false, 1, ConvertOmodMul}, - {"div", AMDGPUOperand::ImmTyOMod, false, 1, ConvertOmodDiv}, -}; - -static bool isVOP3(OperandVector &Operands) { - if (operandsHaveModifiers(Operands)) +static bool ConvertBoundCtrl(int64_t &BoundCtrl) { + if (BoundCtrl == 0) { + BoundCtrl = 1; + return true; + } else if (BoundCtrl == -1) { + BoundCtrl = 0; return true; - - if (Operands.size() >= 2) { - AMDGPUOperand &DstOp = ((AMDGPUOperand&)*Operands[1]); - - if (DstOp.isRegClass(AMDGPU::SGPR_64RegClassID)) - return true; } + return false; +} - if (Operands.size() >= 5) - return true; +// Note: the order in this table matches the order of operands in AsmString. +static const OptionalOperand AMDGPUOperandTable[] = { + {"offen", AMDGPUOperand::ImmTyOffen, true, 0, nullptr}, + {"offset0", AMDGPUOperand::ImmTyOffset0, false, 0, nullptr}, + {"offset1", AMDGPUOperand::ImmTyOffset1, false, 0, nullptr}, + {"gds", AMDGPUOperand::ImmTyGDS, true, 0, nullptr}, + {"offset", AMDGPUOperand::ImmTyOffset, false, 0, nullptr}, + {"glc", AMDGPUOperand::ImmTyGLC, true, 0, nullptr}, + {"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr}, + {"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr}, + {"clamp", AMDGPUOperand::ImmTyClampSI, true, 0, nullptr}, + {"omod", AMDGPUOperand::ImmTyOModSI, false, 1, ConvertOmodMul}, + {"unorm", AMDGPUOperand::ImmTyUNorm, true, 0, nullptr}, + {"da", AMDGPUOperand::ImmTyDA, true, 0, nullptr}, + {"r128", AMDGPUOperand::ImmTyR128, true, 0, nullptr}, + {"lwe", AMDGPUOperand::ImmTyLWE, true, 0, nullptr}, + {"dmask", AMDGPUOperand::ImmTyDMask, false, 0, nullptr}, + {"dpp_ctrl", AMDGPUOperand::ImmTyDppCtrl, false, -1, nullptr}, + {"row_mask", AMDGPUOperand::ImmTyDppRowMask, false, 0xf, nullptr}, + {"bank_mask", AMDGPUOperand::ImmTyDppBankMask, false, 0xf, nullptr}, + {"bound_ctrl", AMDGPUOperand::ImmTyDppBoundCtrl, false, -1, ConvertBoundCtrl}, +}; - if (Operands.size() > 3) { - AMDGPUOperand &Src1Op = ((AMDGPUOperand&)*Operands[3]); - if (Src1Op.isRegClass(AMDGPU::SReg_32RegClassID) || - Src1Op.isRegClass(AMDGPU::SReg_64RegClassID)) - return true; +AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands, const OptionalOperand& Op, bool AddDefault) +{ + if (Op.IsBit) { + return parseNamedBit(Op.Name, Operands, Op.Type, AddDefault); + } else if (Op.Type == AMDGPUOperand::ImmTyDppCtrl) { + return parseDPPCtrlOps(Operands, AddDefault); + } else if (Op.Type == AMDGPUOperand::ImmTyOModSI) { + return parseOModOperand(Operands); + } else { + return parseIntWithPrefix(Op.Name, Operands, Op.Type, Op.Default, AddDefault, Op.ConvertResult); } - return false; } -AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseVOP3OptionalOps(OperandVector &Operands) { - - // The value returned by this function may change after parsing - // an operand so store the original value here. - bool HasModifiers = operandsHaveModifiers(Operands); - - bool IsVOP3 = isVOP3(Operands); - if (HasModifiers || IsVOP3 || - getLexer().isNot(AsmToken::EndOfStatement) || - getForcedEncodingSize() == 64) { - - AMDGPUAsmParser::OperandMatchResultTy Res = - parseOptionalOps(VOP3OptionalOps, Operands); - - if (!HasModifiers && Res == MatchOperand_Success) { - // We have added a modifier operation, so we need to make sure all - // previous register operands have modifiers - for (unsigned i = 2, e = Operands.size(); i != e; ++i) { - AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]); - if ((Op.isReg() || Op.isImm()) && !Op.hasModifiers()) - Op.setModifiers(0); - } +AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseAMDGPUOperand(OperandVector &Operands, StringRef Name) +{ + StringRef Tok; + if (getLexer().is(AsmToken::Identifier)) { + Tok = Parser.getTok().getString(); + } + bool optional = false; + if (Tok == "mul" || Tok == "div") { optional = true; } + for (const OptionalOperand &Op1 : AMDGPUOperandTable) { + if (Op1.Name == Tok) { optional = true; break; } + } + // Attemp to parse current optional operand. + for (const OptionalOperand &Op : AMDGPUOperandTable) { + // TODO: For now, omod is handled separately because + // token name does not match name in table. + bool parseThis = + Name == "" || + (Op.Name == Name) || + (Name == "omod" && Op.Type == AMDGPUOperand::ImmTyOModSI); + if (parseThis && Tok == Name) { + // Exactly the expected token for optional operand. + // Parse it and add operand normally. + return parseOptionalOperand(Operands, Op, true); + } else if (parseThis) { + // Token for optional operand which is later in the table + // than the one we expect. If needed, add default value + // for the operand we expect, do not consume anything + // and return MatchOperand_NoMatch. Parsing will continue. + return parseOptionalOperand(Operands, Op, optional); + } else if (Op.Name == Tok) { + // This looks like optional operand, but we do not expect it. + // This is the case when AsmString has token in it. + return MatchOperand_NoMatch; } - return Res; } return MatchOperand_NoMatch; } +AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands) +{ + StringRef Name = Parser.getTok().getString(); + if (Name == "mul") { + return parseIntWithPrefix("mul", Operands, AMDGPUOperand::ImmTyOModSI, 0, false, ConvertOmodMul); + } else if (Name == "div") { + return parseIntWithPrefix("div", Operands, AMDGPUOperand::ImmTyOModSI, 0, false, ConvertOmodDiv); + } else { + return MatchOperand_NoMatch; + } +} + void AMDGPUAsmParser::cvtId(MCInst &Inst, const OperandVector &Operands) { unsigned I = 1; const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); @@ -2080,8 +2085,8 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) { } } - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClamp); - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOMod); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI); } void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands) { @@ -2110,11 +2115,11 @@ void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands) { addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC); - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE); - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA); } void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) { @@ -2178,7 +2183,7 @@ bool AMDGPUOperand::isDPPCtrl() const { } AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseDPPCtrlOps(OperandVector &Operands) { +AMDGPUAsmParser::parseDPPCtrlOps(OperandVector &Operands, bool AddDefault) { SMLoc S = Parser.getTok().getLoc(); StringRef Prefix; int64_t Int; @@ -2204,7 +2209,12 @@ AMDGPUAsmParser::parseDPPCtrlOps(OperandVector &Operands) { && Prefix != "wave_shr" && Prefix != "wave_ror" && Prefix != "row_bcast") { - return MatchOperand_NoMatch; + if (AddDefault) { + Operands.push_back(AMDGPUOperand::CreateImm(0, S, AMDGPUOperand::ImmTyDppCtrl)); + return MatchOperand_Success; + } else { + return MatchOperand_NoMatch; + } } Parser.Lex(); @@ -2289,30 +2299,6 @@ AMDGPUAsmParser::parseDPPCtrlOps(OperandVector &Operands) { return MatchOperand_Success; } -static const OptionalOperand DPPOptionalOps [] = { - {"row_mask", AMDGPUOperand::ImmTyDppRowMask, false, 0xf, nullptr}, - {"bank_mask", AMDGPUOperand::ImmTyDppBankMask, false, 0xf, nullptr}, - {"bound_ctrl", AMDGPUOperand::ImmTyDppBoundCtrl, false, -1, nullptr} -}; - -AMDGPUAsmParser::OperandMatchResultTy -AMDGPUAsmParser::parseDPPOptionalOps(OperandVector &Operands) { - SMLoc S = Parser.getTok().getLoc(); - OperandMatchResultTy Res = parseOptionalOps(DPPOptionalOps, Operands); - // XXX - sp3 use syntax "bound_ctrl:0" to indicate that bound_ctrl bit was set - if (Res == MatchOperand_Success) { - AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands.back()); - // If last operand was parsed as bound_ctrl we should replace it with correct value (1) - if (Op.isImmTy(AMDGPUOperand::ImmTyDppBoundCtrl)) { - Operands.pop_back(); - Operands.push_back( - AMDGPUOperand::CreateImm(1, S, AMDGPUOperand::ImmTyDppBoundCtrl)); - return MatchOperand_Success; - } - } - return Res; -} - void AMDGPUAsmParser::cvtDPP_mod(MCInst &Inst, const OperandVector &Operands) { cvtDPP(Inst, Operands, true); } diff --git a/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp index 1ea8c77be69..37acd2eb529 100644 --- a/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp @@ -94,7 +94,7 @@ void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo, } } -void AMDGPUInstPrinter::printDSOffset(const MCInst *MI, unsigned OpNo, +void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O) { uint16_t Imm = MI->getOperand(OpNo).getImm(); if (Imm != 0) { @@ -103,7 +103,7 @@ void AMDGPUInstPrinter::printDSOffset(const MCInst *MI, unsigned OpNo, } } -void AMDGPUInstPrinter::printDSOffset0(const MCInst *MI, unsigned OpNo, +void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo, raw_ostream &O) { if (MI->getOperand(OpNo).getImm()) { O << " offset0:"; @@ -111,7 +111,7 @@ void AMDGPUInstPrinter::printDSOffset0(const MCInst *MI, unsigned OpNo, } } -void AMDGPUInstPrinter::printDSOffset1(const MCInst *MI, unsigned OpNo, +void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo, raw_ostream &O) { if (MI->getOperand(OpNo).getImm()) { O << " offset1:"; @@ -119,6 +119,16 @@ void AMDGPUInstPrinter::printDSOffset1(const MCInst *MI, unsigned OpNo, } } +void AMDGPUInstPrinter::printSMRDOffset(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + printU32ImmOperand(MI, OpNo, O); +} + +void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + printU32ImmOperand(MI, OpNo, O); +} + void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo, raw_ostream &O) { printNamedBit(MI, OpNo, O, "gds"); @@ -422,7 +432,7 @@ void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo, } -void AMDGPUInstPrinter::printDPPCtrlOperand(const MCInst *MI, unsigned OpNo, +void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo, raw_ostream &O) { unsigned Imm = MI->getOperand(OpNo).getImm(); if (Imm <= 0x0ff) { @@ -461,19 +471,19 @@ void AMDGPUInstPrinter::printDPPCtrlOperand(const MCInst *MI, unsigned OpNo, } } -void AMDGPUInstPrinter::printRowMaskOperand(const MCInst *MI, unsigned OpNo, +void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << " row_mask:"; printU4ImmOperand(MI, OpNo, O); } -void AMDGPUInstPrinter::printBankMaskOperand(const MCInst *MI, unsigned OpNo, +void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << " bank_mask:"; printU4ImmOperand(MI, OpNo, O); } -void AMDGPUInstPrinter::printBoundCtrlOperand(const MCInst *MI, unsigned OpNo, +void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo, raw_ostream &O) { unsigned Imm = MI->getOperand(OpNo).getImm(); if (Imm) { diff --git a/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h index 97c9c7614a7..e04edc7fec5 100644 --- a/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h @@ -45,9 +45,11 @@ private: void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printAddr64(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printMBUFOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printDSOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printDSOffset0(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printDSOffset1(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printOffset0(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printOffset1(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printSMRDOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printGDS(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printGLC(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printSLC(const MCInst *MI, unsigned OpNo, raw_ostream &O); @@ -63,10 +65,10 @@ private: void printImmediate64(uint64_t I, raw_ostream &O); void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printOperandAndMods(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printDPPCtrlOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printRowMaskOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printBankMaskOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printBoundCtrlOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printDPPCtrl(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printRowMask(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printBankMask(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printBoundCtrl(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printSDWASel(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printSDWADstSel(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printSDWASrc0Sel(const MCInst *MI, unsigned OpNo, raw_ostream &O); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 105ec8a5ecd..8f8533daa1e 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -461,322 +461,75 @@ def const_ga : Operand<iPTR>; include "SIInstrFormats.td" include "VIInstrFormats.td" -def MubufOffsetMatchClass : AsmOperandClass { - let Name = "MubufOffset"; - let ParserMethod = "parseMubufOptionalOps"; +class NamedMatchClass<string CName, bit Optional = 1> : AsmOperandClass { + let Name = "Imm"#CName; + let PredicateMethod = "is"#CName; + let ParserMethod = "parse"#CName; let RenderMethod = "addImmOperands"; - let IsOptional = 1; + let IsOptional = Optional; } -class DSOffsetBaseMatchClass <string parser> : AsmOperandClass { - let Name = "DSOffset"#parser; - let ParserMethod = parser; - let RenderMethod = "addImmOperands"; - let PredicateMethod = "isDSOffset"; - let IsOptional = 1; -} - -def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">; -def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">; - -def DSOffset01MatchClass : AsmOperandClass { - let Name = "DSOffset1"; - let ParserMethod = "parseDSOff01OptionalOps"; - let RenderMethod = "addImmOperands"; - let PredicateMethod = "isDSOffset01"; - let IsOptional = 1; -} - -class GDSBaseMatchClass <string parser> : AsmOperandClass { - let Name = "GDS"#parser; - let PredicateMethod = "isGDS"; - let ParserMethod = parser; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; -} - -def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">; -def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">; - -class GLCBaseMatchClass <string parser> : AsmOperandClass { - let Name = "GLC"#parser; - let PredicateMethod = "isGLC"; - let ParserMethod = parser; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; -} - -def GLCMubufMatchClass : GLCBaseMatchClass <"parseMubufOptionalOps">; -def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">; - -class SLCBaseMatchClass <string parser> : AsmOperandClass { - let Name = "SLC"#parser; - let PredicateMethod = "isSLC"; - let ParserMethod = parser; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; -} - -def SLCMubufMatchClass : SLCBaseMatchClass <"parseMubufOptionalOps">; -def SLCFlatMatchClass : SLCBaseMatchClass <"parseFlatOptionalOps">; -def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">; - -class TFEBaseMatchClass <string parser> : AsmOperandClass { - let Name = "TFE"#parser; - let PredicateMethod = "isTFE"; - let ParserMethod = parser; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; -} - -def TFEMubufMatchClass : TFEBaseMatchClass <"parseMubufOptionalOps">; -def TFEFlatMatchClass : TFEBaseMatchClass <"parseFlatOptionalOps">; -def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">; - -def OModMatchClass : AsmOperandClass { - let Name = "OMod"; - let PredicateMethod = "isOMod"; - let ParserMethod = "parseVOP3OptionalOps"; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; -} +def sdwa_sel : NamedMatchClass<"SDWASel">; -def ClampMatchClass : AsmOperandClass { - let Name = "Clamp"; - let PredicateMethod = "isClamp"; - let ParserMethod = "parseVOP3OptionalOps"; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; +class NamedOperandBit<string Name, AsmOperandClass MatchClass> : Operand<i1> { + let PrintMethod = "print"#Name; + let ParserMatchClass = MatchClass; } - -class SMRDOffsetBaseMatchClass <string predicate> : AsmOperandClass { - let Name = "SMRDOffset"#predicate; - let PredicateMethod = predicate; - let RenderMethod = "addImmOperands"; + +class NamedOperandU8<string Name, AsmOperandClass MatchClass> : Operand<i8> { + let PrintMethod = "print"#Name; + let ParserMatchClass = MatchClass; } -def SMRDOffsetMatchClass : SMRDOffsetBaseMatchClass <"isSMRDOffset">; -def SMRDLiteralOffsetMatchClass : SMRDOffsetBaseMatchClass < - "isSMRDLiteralOffset" ->; - -def DPPCtrlMatchClass : AsmOperandClass { - let Name = "DPPCtrl"; - let PredicateMethod = "isDPPCtrl"; - let ParserMethod = "parseDPPCtrlOps"; - let RenderMethod = "addImmOperands"; - let IsOptional = 0; +class NamedOperandU16<string Name, AsmOperandClass MatchClass> : Operand<i16> { + let PrintMethod = "print"#Name; + let ParserMatchClass = MatchClass; } -class DPPOptionalMatchClass <string OpName>: AsmOperandClass { - let Name = "DPPOptional"#OpName; - let PredicateMethod = "is"#OpName; - let ParserMethod = "parseDPPOptionalOps"; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; -} - -def SDWASelMatchClass : AsmOperandClass { - let Name = "SDWASel"; - let PredicateMethod = "isSDWASel"; - let ParserMethod = "parseSDWASel"; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; -} - -def SDWADstUnusedMatchClass : AsmOperandClass { - let Name = "SDWADstUnused"; - let PredicateMethod = "isSDWADstUnused"; - let ParserMethod = "parseSDWADstUnused"; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; -} - -class OptionalImmAsmOperand <string OpName> : AsmOperandClass { - let Name = "Imm"#OpName; - let PredicateMethod = "isImm"; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; -} - -def DMaskMatchClass : AsmOperandClass { - let Name = "DMask"; - let PredicateMethod = "isDMask"; - let ParserMethod = "parseDMask"; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; -} - -class NamedBitMatchClass<string BitName> : AsmOperandClass { - let Name = "Imm"#BitName; - let PredicateMethod = "is"#BitName; - let ParserMethod = "parse"#BitName; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; -} - -class NamedBitOperand<string BitName> : Operand<i1> { - let PrintMethod = "print"#BitName; -} - -def HwregMatchClass : AsmOperandClass { - let Name = "Hwreg"; - let PredicateMethod = "isHwreg"; - let ParserMethod = "parseHwregOp"; - let RenderMethod = "addImmOperands"; +class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> { + let PrintMethod = "print"#Name; + let ParserMatchClass = MatchClass; } let OperandType = "OPERAND_IMMEDIATE" in { -def offen : Operand<i1> { - let PrintMethod = "printOffen"; - let ParserMatchClass = OptionalImmAsmOperand<"offen">; -} -def idxen : Operand<i1> { - let PrintMethod = "printIdxen"; - let ParserMatchClass = OptionalImmAsmOperand<"idxen">; -} -def addr64 : Operand<i1> { - let PrintMethod = "printAddr64"; -} -def mbuf_offset : Operand<i16> { - let PrintMethod = "printMBUFOffset"; - let ParserMatchClass = MubufOffsetMatchClass; -} -class ds_offset_base <AsmOperandClass mc> : Operand<i16> { - let PrintMethod = "printDSOffset"; - let ParserMatchClass = mc; -} -def ds_offset : ds_offset_base <DSOffsetMatchClass>; -def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>; +def offen : NamedOperandBit<"Offen", NamedMatchClass<"Offen">>; +def idxen : NamedOperandBit<"Idxen", NamedMatchClass<"Idxen">>; +def addr64 : NamedOperandBit<"Addr64", NamedMatchClass<"Addr64">>; -def ds_offset0 : Operand<i8> { - let PrintMethod = "printDSOffset0"; - let ParserMatchClass = DSOffset01MatchClass; -} -def ds_offset1 : Operand<i8> { - let PrintMethod = "printDSOffset1"; - let ParserMatchClass = DSOffset01MatchClass; -} -class gds_base <AsmOperandClass mc> : Operand <i1> { - let PrintMethod = "printGDS"; - let ParserMatchClass = mc; -} -def gds : gds_base <GDSMatchClass>; +def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>; +def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>; +def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>; -def gds01 : gds_base <GDS01MatchClass>; +def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>; -class glc_base <AsmOperandClass mc> : Operand <i1> { - let PrintMethod = "printGLC"; - let ParserMatchClass = mc; -} +def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>; +def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>; -def glc : glc_base <GLCMubufMatchClass>; -def glc_flat : glc_base <GLCFlatMatchClass>; +def smrd_offset : NamedOperandU32<"SMRDOffset", NamedMatchClass<"SMRDOffset">>; +def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset", NamedMatchClass<"SMRDLiteralOffset">>; -class slc_base <AsmOperandClass mc> : Operand <i1> { - let PrintMethod = "printSLC"; - let ParserMatchClass = mc; -} +def glc : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>; +def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>; +def tfe : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>; +def unorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>; +def da : NamedOperandBit<"DA", NamedMatchClass<"DA">>; +def r128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>; +def lwe : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>; -def slc : slc_base <SLCMubufMatchClass>; -def slc_flat : slc_base <SLCFlatMatchClass>; -def slc_flat_atomic : slc_base <SLCFlatAtomicMatchClass>; +def dmask : NamedOperandU16<"DMask", NamedMatchClass<"DMask">>; -class tfe_base <AsmOperandClass mc> : Operand <i1> { - let PrintMethod = "printTFE"; - let ParserMatchClass = mc; -} +def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>; +def row_mask : NamedOperandU32<"RowMask", NamedMatchClass<"RowMask">>; +def bank_mask : NamedOperandU32<"BankMask", NamedMatchClass<"BankMask">>; +def bound_ctrl : NamedOperandBit<"BoundCtrl", NamedMatchClass<"BoundCtrl">>; -def tfe : tfe_base <TFEMubufMatchClass>; -def tfe_flat : tfe_base <TFEFlatMatchClass>; -def tfe_flat_atomic : tfe_base <TFEFlatAtomicMatchClass>; +def dst_sel : NamedOperandU32<"SDWADstSel", sdwa_sel>; +def src0_sel : NamedOperandU32<"SDWASrc0Sel", sdwa_sel>; +def src1_sel : NamedOperandU32<"SDWASrc1Sel", sdwa_sel>; +def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused">>; -def omod : Operand <i32> { - let PrintMethod = "printOModSI"; - let ParserMatchClass = OModMatchClass; -} - -def ClampMod : Operand <i1> { - let PrintMethod = "printClampSI"; - let ParserMatchClass = ClampMatchClass; -} - -def smrd_offset : Operand <i32> { - let PrintMethod = "printU32ImmOperand"; - let ParserMatchClass = SMRDOffsetMatchClass; -} - -def smrd_literal_offset : Operand <i32> { - let PrintMethod = "printU32ImmOperand"; - let ParserMatchClass = SMRDLiteralOffsetMatchClass; -} - -def dmask : Operand <i32> { - let PrintMethod = "printDMask"; - let ParserMatchClass = DMaskMatchClass; -} - -def unorm : NamedBitOperand<"UNorm"> { - let ParserMatchClass = NamedBitMatchClass<"UNorm">; -} - -def da : NamedBitOperand<"DA"> { - let ParserMatchClass = NamedBitMatchClass<"DA">; -} - -def r128 : NamedBitOperand<"R128"> { - let ParserMatchClass = NamedBitMatchClass<"R128">; -} - -def lwe : NamedBitOperand<"LWE"> { - let ParserMatchClass = NamedBitMatchClass<"LWE">; -} - -def dpp_ctrl : Operand <i32> { - let PrintMethod = "printDPPCtrlOperand"; - let ParserMatchClass = DPPCtrlMatchClass; -} - -def row_mask : Operand <i32> { - let PrintMethod = "printRowMaskOperand"; - let ParserMatchClass = DPPOptionalMatchClass<"RowMask">; -} - -def bank_mask : Operand <i32> { - let PrintMethod = "printBankMaskOperand"; - let ParserMatchClass = DPPOptionalMatchClass<"BankMask">; -} - -def bound_ctrl : Operand <i1> { - let PrintMethod = "printBoundCtrlOperand"; - let ParserMatchClass = DPPOptionalMatchClass<"BoundCtrl">; -} - -def dst_sel : Operand <i32> { - let PrintMethod = "printSDWADstSel"; - let ParserMatchClass = SDWASelMatchClass; -} - -def src0_sel : Operand <i32> { - let PrintMethod = "printSDWASrc0Sel"; - let ParserMatchClass = SDWASelMatchClass; -} - -def src1_sel : Operand <i32> { - let PrintMethod = "printSDWASrc1Sel"; - let ParserMatchClass = SDWASelMatchClass; -} - -def hwreg : Operand <i16> { - let PrintMethod = "printHwreg"; - let ParserMatchClass = HwregMatchClass; -} - -def dst_unused : Operand <i32> { - let PrintMethod = "printSDWADstUnused"; - let ParserMatchClass = SDWADstUnusedMatchClass; -} +def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg">>; } // End OperandType = "OPERAND_IMMEDIATE" @@ -1401,7 +1154,7 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC, !if (!eq(HasModifiers, 1), // VOP1 with modifiers (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, - ClampMod:$clamp, omod:$omod) + clampmod:$clamp, omod:$omod) /* else */, // VOP1 without modifiers (ins Src0RC:$src0) @@ -1411,7 +1164,7 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC, // VOP 2 with modifiers (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, InputModsNoDefault:$src1_modifiers, Src1RC:$src1, - ClampMod:$clamp, omod:$omod) + clampmod:$clamp, omod:$omod) /* else */, // VOP2 without modifiers (ins Src0RC:$src0, Src1RC:$src1) @@ -1422,7 +1175,7 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC, (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, InputModsNoDefault:$src1_modifiers, Src1RC:$src1, InputModsNoDefault:$src2_modifiers, Src2RC:$src2, - ClampMod:$clamp, omod:$omod) + clampmod:$clamp, omod:$omod) /* else */, // VOP3 without modifiers (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2) @@ -1472,7 +1225,7 @@ class getInsSDWA <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs, !if (!eq(HasModifiers, 1), // VOP1_SDWA with modifiers (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, - ClampMod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, + clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, src0_sel:$src0_sel) /* else */, // VOP1_SDWA without modifiers @@ -1484,7 +1237,7 @@ class getInsSDWA <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs, // VOP2_SDWA with modifiers (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, InputModsNoDefault:$src1_modifiers, Src1RC:$src1, - ClampMod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, + clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, src0_sel:$src0_sel, src1_sel:$src1_sel) /* else */, // VOP2_DPP without modifiers @@ -1545,7 +1298,7 @@ class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = string args = !if(!eq(HasModifiers, 0), getAsm32<0, NumSrcArgs, DstVT>.ret, ", "#src0#src1); - string ret = dst#args#" $dpp_ctrl $row_mask $bank_mask $bound_ctrl"; + string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; } class getAsmSDWA <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> { @@ -1769,7 +1522,7 @@ def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> { let InsSDWA = (ins InputModsNoDefault:$src0_modifiers, Src0RC32:$src0, InputModsNoDefault:$src1_modifiers, Src1RC32:$src1, VGPR_32:$src2, // stub argument - ClampMod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, + clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, src0_sel:$src0_sel, src1_sel:$src1_sel); let Asm32 = getAsm32<1, 2, f32>.ret; let Asm64 = getAsm64<1, 2, HasModifiers, f32>.ret; @@ -2548,7 +2301,7 @@ multiclass VOP3_VCC_Inst <vop3 op, string opName, (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0, InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1, InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2, - ClampMod:$clamp, + clampmod:$clamp, omod:$omod), "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", [(set P.DstVT:$vdst, @@ -2668,7 +2421,7 @@ class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc, dag outs = (outs rc:$vdst), - dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds), + dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds), string asm = opName#" $vdst, $addr"#"$offset$gds"> { def "" : DS_Pseudo <opName, outs, ins, []>; @@ -2681,8 +2434,8 @@ multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc, multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc, dag outs = (outs rc:$vdst), - dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1, - gds01:$gds), + dag ins = (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, + gds:$gds), string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> { def "" : DS_Pseudo <opName, outs, ins, []>; @@ -2695,7 +2448,7 @@ multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc, multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc, dag outs = (outs), - dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds), + dag ins = (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds), string asm = opName#" $addr, $data0"#"$offset$gds"> { def "" : DS_Pseudo <opName, outs, ins, []>, @@ -2710,8 +2463,8 @@ multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc, multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc, dag outs = (outs), dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1, - ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds), - string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> { + offset0:$offset0, offset1:$offset1, gds:$gds), + string asm = opName#" $addr, $data0, $data1$offset0$offset1$gds"> { def "" : DS_Pseudo <opName, outs, ins, []>; @@ -2724,7 +2477,7 @@ multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc, multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc, string noRetOp = "", dag outs = (outs rc:$vdst), - dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds), + dag ins = (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds), string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> { let hasPostISelHook = 1 in { @@ -2773,14 +2526,14 @@ multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = "", RegisterClass src = rc> : DS_1A2D_RET_m <op, asm, rc, noRetOp, (ins VGPR_32:$addr, src:$data0, src:$data1, - ds_offset:$offset, gds:$gds) + offset:$offset, gds:$gds) >; multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc, string noRetOp = opName, dag outs = (outs), dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1, - ds_offset:$offset, gds:$gds), + offset:$offset, gds:$gds), string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> { def "" : DS_Pseudo <opName, outs, ins, []>, @@ -2794,7 +2547,7 @@ multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc, multiclass DS_0A_RET <bits<8> op, string opName, dag outs = (outs VGPR_32:$vdst), - dag ins = (ins ds_offset:$offset, gds:$gds), + dag ins = (ins offset:$offset, gds:$gds), string asm = opName#" $vdst"#"$offset"#"$gds"> { let mayLoad = 1, mayStore = 1 in { @@ -2809,7 +2562,7 @@ multiclass DS_0A_RET <bits<8> op, string opName, multiclass DS_1A_RET_GDS <bits<8> op, string opName, dag outs = (outs VGPR_32:$vdst), - dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset), + dag ins = (ins VGPR_32:$addr, offset:$offset), string asm = opName#" $vdst, $addr"#"$offset gds"> { def "" : DS_Pseudo <opName, outs, ins, []>; @@ -2835,7 +2588,7 @@ multiclass DS_1A_GDS <bits<8> op, string opName, multiclass DS_1A <bits<8> op, string opName, dag outs = (outs), - dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds), + dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds), string asm = opName#" $addr"#"$offset"#"$gds"> { let mayLoad = 1, mayStore = 1 in { @@ -3065,23 +2818,23 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc, defm _ADDR64 : MUBUFAtomicAddr64_m < op, name#"_addr64", (outs), (ins rc:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc), - name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0 + SCSrc_32:$soffset, offset:$offset, slc:$slc), + name#" $vdata, $vaddr, $srsrc, $soffset addr64$offset$slc", [], 0 >; defm _OFFSET : MUBUFAtomicOffset_m < op, name#"_offset", (outs), - (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset, + (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, offset:$offset, slc:$slc), - name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0 + name#" $vdata, off, $srsrc, $soffset$offset$slc", [], 0 >; let offen = 1, idxen = 0 in { defm _OFFEN : MUBUFAtomicOther_m < op, name#"_offen", (outs), (ins rc:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, slc:$slc), - name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$slc", [], 0 + offset:$offset, slc:$slc), + name#" $vdata, $vaddr, $srsrc, $soffset offen$offset$slc", [], 0 >; } @@ -3089,8 +2842,8 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc, defm _IDXEN : MUBUFAtomicOther_m < op, name#"_idxen", (outs), (ins rc:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, slc:$slc), - name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$slc", [], 0 + offset:$offset, slc:$slc), + name#" $vdata, $vaddr, $srsrc, $soffset idxen$offset$slc", [], 0 >; } @@ -3098,8 +2851,8 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc, defm _BOTHEN : MUBUFAtomicOther_m < op, name#"_bothen", (outs), (ins rc:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, slc:$slc), - name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$slc", + offset:$offset, slc:$slc), + name#" $vdata, $vaddr, $srsrc, $soffset idxen offen$offset$slc", [], 0 >; } @@ -3112,7 +2865,7 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc, defm _RTN_ADDR64 : MUBUFAtomicAddr64_m < op, name#"_rtn_addr64", (outs rc:$vdata), (ins rc:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc), + SCSrc_32:$soffset, offset:$offset, slc:$slc), name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc", [(set vt:$vdata, (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset, @@ -3122,8 +2875,8 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc, defm _RTN_OFFSET : MUBUFAtomicOffset_m < op, name#"_rtn_offset", (outs rc:$vdata), (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, slc:$slc), - name#" $vdata, $srsrc, $soffset"#"$offset"#" glc$slc", + offset:$offset, slc:$slc), + name#" $vdata, off, $srsrc, $soffset $offset glc$slc", [(set vt:$vdata, (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$slc), vt:$vdata_in))], 1 @@ -3133,7 +2886,7 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc, defm _RTN_OFFEN : MUBUFAtomicOther_m < op, name#"_rtn_offen", (outs rc:$vdata), (ins rc:$vdata_in, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, slc:$slc), + offset:$offset, slc:$slc), name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#" glc"#"$slc", [], 1 >; @@ -3143,7 +2896,7 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc, defm _RTN_IDXEN : MUBUFAtomicOther_m < op, name#"_rtn_idxen", (outs rc:$vdata), (ins rc:$vdata_in, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, slc:$slc), + offset:$offset, slc:$slc), name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#" glc"#"$slc", [], 1 >; @@ -3153,7 +2906,7 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc, defm _RTN_BOTHEN : MUBUFAtomicOther_m < op, name#"_rtn_bothen", (outs rc:$vdata), (ins rc:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, slc:$slc), + offset:$offset, slc:$slc), name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#" glc"#"$slc", [], 1 >; @@ -3173,8 +2926,8 @@ multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass, let offen = 0, idxen = 0, vaddr = 0 in { defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata), (ins SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe", + offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), + name#" $vdata, off, $srsrc, $soffset$offset$glc$slc$tfe", [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))]>; @@ -3183,33 +2936,32 @@ multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass, let offen = 1, idxen = 0 in { defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata), (ins VGPR_32:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc, + SCSrc_32:$soffset, offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; + name#" $vdata, $vaddr, $srsrc, $soffset offen$offset$glc$slc$tfe", []>; } let offen = 0, idxen = 1 in { defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata), (ins VGPR_32:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, + SCSrc_32:$soffset, offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; + name#" $vdata, $vaddr, $srsrc, $soffset idxen$offset$glc$slc$tfe", []>; } let offen = 1, idxen = 1 in { defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata), (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; + offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), + name#" $vdata, $vaddr, $srsrc, $soffset idxen offen$offset$glc$slc$tfe", []>; } let offen = 0, idxen = 0 in { defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata), (ins VReg_64:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, + SCSrc_32:$soffset, offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"# - "$glc"#"$slc"#"$tfe", + name#" $vdata, $vaddr, $srsrc, $soffset addr64$offset$glc$slc$tfe", [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, @@ -3221,18 +2973,11 @@ multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass, multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass, ValueType store_vt = i32, SDPatternOperator st = null_frag> { let mayLoad = 0, mayStore = 1 in { - defm : MUBUF_m <op, name, (outs), - (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc, - tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"# - "$glc"#"$slc"#"$tfe", []>; - let offen = 0, idxen = 0, vaddr = 0 in { defm _OFFSET : MUBUF_m <op, name#"_offset",(outs), (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe", + offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), + name#" $vdata, off, $srsrc, $soffset$offset$glc$slc$tfe", [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>; } // offen = 0, idxen = 0, vaddr = 0 @@ -3240,35 +2985,35 @@ multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass, let offen = 1, idxen = 0 in { defm _OFFEN : MUBUF_m <op, name#"_offen", (outs), (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, + SCSrc_32:$soffset, offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"# - "$glc"#"$slc"#"$tfe", []>; + name#" $vdata, $vaddr, $srsrc, $soffset offen"# + "$offset$glc$slc$tfe", []>; } // end offen = 1, idxen = 0 let offen = 0, idxen = 1 in { defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs), (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, + SCSrc_32:$soffset, offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; + name#" $vdata, $vaddr, $srsrc, $soffset idxen$offset$glc$slc$tfe", []>; } let offen = 1, idxen = 1 in { defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs), (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; + offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), + name#" $vdata, $vaddr, $srsrc, $soffset idxen offen$offset$glc$slc$tfe", []>; } let offen = 0, idxen = 0 in { defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs), (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, glc:$glc, slc:$slc, + offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), name#" $vdata, $vaddr, $srsrc, $soffset addr64"# - "$offset"#"$glc"#"$slc"#"$tfe", + "$offset$glc$slc$tfe", [(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, @@ -3338,8 +3083,8 @@ multiclass FLAT_AtomicRet_m <flat op, dag outs, dag ins, string asm, multiclass FLAT_Load_Helper <flat op, string asm_name, RegisterClass regClass, dag outs = (outs regClass:$vdst), - dag ins = (ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe), - string asm = asm_name#" $vdst, $addr"#"$glc"#"$slc"#"$tfe"> { + dag ins = (ins VReg_64:$addr, glc:$glc, slc:$slc, tfe:$tfe), + string asm = asm_name#" $vdst, $addr$glc$slc$tfe"> { let data = 0, mayLoad = 1 in { @@ -3354,9 +3099,9 @@ multiclass FLAT_Load_Helper <flat op, string asm_name, multiclass FLAT_Store_Helper <flat op, string asm_name, RegisterClass vdataClass, dag outs = (outs), - dag ins = (ins VReg_64:$addr, vdataClass:$data, glc_flat:$glc, - slc_flat:$slc, tfe_flat:$tfe), - string asm = asm_name#" $addr, $data"#"$glc"#"$slc"#"$tfe"> { + dag ins = (ins VReg_64:$addr, vdataClass:$data, glc:$glc, + slc:$slc, tfe:$tfe), + string asm = asm_name#" $addr, $data$glc$slc$tfe"> { let mayLoad = 0, mayStore = 1, vdst = 0 in { @@ -3376,25 +3121,25 @@ multiclass FLAT_ATOMIC <flat op, string asm_name, RegisterClass vdst_rc, let mayLoad = 1, mayStore = 1, glc = 0, vdst = 0, AsmMatchConverter = "cvtFlatAtomic" in { def "" : FLAT_Pseudo <NAME, outs_noret, (ins VReg_64:$addr, data_rc:$data, - slc_flat_atomic:$slc, tfe_flat_atomic:$tfe), []>, + slc:$slc, tfe:$tfe), []>, AtomicNoRet <NAME, 0>; def _ci : FLAT_Real_ci <op.CI, NAME, outs_noret, (ins VReg_64:$addr, data_rc:$data, - slc_flat_atomic:$slc, tfe_flat_atomic:$tfe), + slc:$slc, tfe:$tfe), asm_noret>; def _vi : FLAT_Real_vi <op.VI, NAME, outs_noret, (ins VReg_64:$addr, data_rc:$data, - slc_flat_atomic:$slc, tfe_flat_atomic:$tfe), + slc:$slc, tfe:$tfe), asm_noret>; } let glc = 1, hasPostISelHook = 1, AsmMatchConverter = "cvtFlatAtomic" in { defm _RTN : FLAT_AtomicRet_m <op, (outs vdst_rc:$vdst), - (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc, - tfe_flat_atomic:$tfe), - asm_name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>; + (ins VReg_64:$addr, data_rc:$data, slc:$slc, + tfe:$tfe), + asm_name#" $vdst, $addr, $data glc$slc$tfe", []>; } } |
