diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/Mips32r6InstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 16 |
4 files changed, 34 insertions, 11 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 6406468c6c4..eff27b75e76 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1138,7 +1138,15 @@ public: (R0 == Mips::A0 && R1 == Mips::S6) || (R0 == Mips::A0 && R1 == Mips::A1) || (R0 == Mips::A0 && R1 == Mips::A2) || - (R0 == Mips::A0 && R1 == Mips::A3)) + (R0 == Mips::A0 && R1 == Mips::A3) || + (R0 == Mips::A1_64 && R1 == Mips::A2_64) || + (R0 == Mips::A1_64 && R1 == Mips::A3_64) || + (R0 == Mips::A2_64 && R1 == Mips::A3_64) || + (R0 == Mips::A0_64 && R1 == Mips::S5_64) || + (R0 == Mips::A0_64 && R1 == Mips::S6_64) || + (R0 == Mips::A0_64 && R1 == Mips::A1_64) || + (R0 == Mips::A0_64 && R1 == Mips::A2_64) || + (R0 == Mips::A0_64 && R1 == Mips::A3_64)) return true; return false; diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 92a4367aa7c..ea5b9c17bf0 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -717,9 +717,15 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>, SRLV_FM_MM<0x90, 0>; def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>, - SRA_FM_MM<0xc0, 0>; + SRA_FM_MM<0xc0, 0> { + list<dag> Pattern = [(set GPR32Opnd:$rd, + (rotr GPR32Opnd:$rt, immZExt5:$shamt))]; + } def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>, - SRLV_FM_MM<0xd0, 0>; + SRLV_FM_MM<0xd0, 0> { + list<dag> Pattern = [(set GPR32Opnd:$rd, + (rotr GPR32Opnd:$rt, GPR32Opnd:$rs))]; + } /// Load and Store Instructions - aligned let DecoderMethod = "DecodeMemMMImm16" in { @@ -1055,4 +1061,7 @@ def : MipsInstAlias<"sra $rd, $shamt", (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; def : MipsInstAlias<"srl $rd, $shamt", (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; +def : MipsInstAlias<"rotr $rt, $imm", + (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>; +def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>; } diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td index ea75cc5bba2..f249ff2d610 100644 --- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td @@ -757,7 +757,9 @@ def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6; def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; -def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; +let AdditionalPredicates = [NotInMicroMips] in { + def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; +} def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6; def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; @@ -791,9 +793,9 @@ def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6; let AdditionalPredicates = [NotInMicroMips] in { def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT; def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT; + def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; } -def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; let AdditionalPredicates = [NotInMicroMips] in { diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index d66f7a3e13d..0539c544a32 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1696,11 +1696,13 @@ def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, } // Rotate Instructions -def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, - immZExt5>, - SRA_FM<2, 1>, ISA_MIPS32R2; -def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, - SRLV_FM<6, 1>, ISA_MIPS32R2; +let AdditionalPredicates = [NotInMicroMips] in { + def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, + immZExt5>, + SRA_FM<2, 1>, ISA_MIPS32R2; + def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, + SRLV_FM<6, 1>, ISA_MIPS32R2; +} /// Load and Store Instructions /// aligned @@ -2215,7 +2217,9 @@ def : MipsInstAlias<"beqz $rs,$offset", (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; def : MipsInstAlias<"beqzl $rs,$offset", (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; -def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; +} def : MipsInstAlias<"break", (BREAK 0, 0), 1>; def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; |
