diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZInstrFormats.td | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZProcessors.td | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZSubtarget.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZSubtarget.h | 4 |
5 files changed, 41 insertions, 3 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td index a8efe165e36..50badf82bc7 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -531,6 +531,10 @@ class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> // Ternary: // One register output operand and three register input operands. // +// LoadAndOp: +// One output operand and two input operands. The first input operand +// is a register and the second is an address. +// // CmpSwap: // One output operand and three input operands. The first two // operands are registers and the third is an address. The instruction @@ -1267,6 +1271,15 @@ class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator, let AccessBytes = bytes; } +class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, + RegisterOperand cls, AddressingMode mode = bdaddr20only> + : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2), + mnemonic#"\t$R1, $R3, $BD2", + [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> { + let mayLoad = 1; + let mayStore = 1; +} + class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, RegisterOperand cls, AddressingMode mode = bdaddr12only> : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2), diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td index 587b170b5ac..91c3d3c3d0d 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -1203,6 +1203,19 @@ def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>; +let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { + def LAA : LoadAndOpRSY<"laa", 0xEBF8, null_frag, GR32>; + def LAAG : LoadAndOpRSY<"laag", 0xEBE8, null_frag, GR64>; + def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; + def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; + def LAN : LoadAndOpRSY<"lan", 0xEBF4, null_frag, GR32>; + def LANG : LoadAndOpRSY<"lang", 0xEBE4, null_frag, GR64>; + def LAO : LoadAndOpRSY<"lao", 0xEBF6, null_frag, GR32>; + def LAOG : LoadAndOpRSY<"laog", 0xEBE6, null_frag, GR64>; + def LAX : LoadAndOpRSY<"lax", 0xEBF7, null_frag, GR32>; + def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, null_frag, GR64>; +} + def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; diff --git a/llvm/lib/Target/SystemZ/SystemZProcessors.td b/llvm/lib/Target/SystemZ/SystemZProcessors.td index 9aed4f9edff..b3df317bc84 100644 --- a/llvm/lib/Target/SystemZ/SystemZProcessors.td +++ b/llvm/lib/Target/SystemZ/SystemZProcessors.td @@ -41,11 +41,18 @@ def FeatureFastSerialization : SystemZFeature< "Assume that the fast-serialization facility is installed" >; +def FeatureInterlockedAccess1 : SystemZFeature< + "interlocked-access1", "InterlockedAccess1", + "Assume that interlocked-access facility 1 is installed" +>; + def : Processor<"generic", NoItineraries, []>; def : Processor<"z10", NoItineraries, []>; def : Processor<"z196", NoItineraries, [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord, - FeatureFPExtension, FeatureFastSerialization]>; + FeatureFPExtension, FeatureFastSerialization, + FeatureInterlockedAccess1]>; def : Processor<"zEC12", NoItineraries, [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord, - FeatureFPExtension, FeatureFastSerialization]>; + FeatureFPExtension, FeatureFastSerialization, + FeatureInterlockedAccess1]>; diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp index 333db2536e7..5a85a043be3 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -26,7 +26,8 @@ SystemZSubtarget::SystemZSubtarget(const std::string &TT, const std::string &FS) : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false), HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false), - HasFastSerialization(false), TargetTriple(TT) { + HasFastSerialization(false), HasInterlockedAccess1(false), + TargetTriple(TT) { std::string CPUName = CPU; if (CPUName.empty()) CPUName = "generic"; diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.h b/llvm/lib/Target/SystemZ/SystemZSubtarget.h index 6823c1432cd..f7c8f96c044 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.h +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.h @@ -33,6 +33,7 @@ protected: bool HasHighWord; bool HasFPExtension; bool HasFastSerialization; + bool HasInterlockedAccess1; private: Triple TargetTriple; @@ -62,6 +63,9 @@ public: // Return true if the target has the fast-serialization facility. bool hasFastSerialization() const { return HasFastSerialization; } + // Return true if the target has interlocked-access facility 1. + bool hasInterlockedAccess1() const { return HasInterlockedAccess1; } + // Return true if GV can be accessed using LARL for reloc model RM // and code model CM. bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM, |
