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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp1
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp13
2 files changed, 10 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
index 0f4a0320f62..f1d92dc7270 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -312,6 +312,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
void FunctionLoweringInfo::clear() {
MBBMap.clear();
ValueMap.clear();
+ VirtReg2Value.clear();
StaticAllocaMap.clear();
LiveOutRegInfo.clear();
VisitedBBs.clear();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index f142ef6b01e..0ede62ba4d4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -806,12 +806,11 @@ bool AMDGPUTargetLowering::isSDNodeSourceOfDivergence(const SDNode * N,
if (MRI.isLiveIn(Reg)) {
// workitem.id.x workitem.id.y workitem.id.z
+ // Any VGPR formal argument is also considered divergent
if ((MRI.getLiveInPhysReg(Reg) == AMDGPU::T0_X) ||
(MRI.getLiveInPhysReg(Reg) == AMDGPU::T0_Y) ||
- (MRI.getLiveInPhysReg(Reg) == AMDGPU::T0_Z)||
- (MRI.getLiveInPhysReg(Reg) == AMDGPU::VGPR0) ||
- (MRI.getLiveInPhysReg(Reg) == AMDGPU::VGPR1) ||
- (MRI.getLiveInPhysReg(Reg) == AMDGPU::VGPR2))
+ (MRI.getLiveInPhysReg(Reg) == AMDGPU::T0_Z) ||
+ (TRI.isVGPR(MRI, Reg)))
return true;
// Formal arguments of non-entry functions
// are conservatively considered divergent
@@ -840,6 +839,12 @@ bool AMDGPUTargetLowering::isSDNodeSourceOfDivergence(const SDNode * N,
case ISD::INTRINSIC_W_CHAIN:
return AMDGPU::isIntrinsicSourceOfDivergence(
cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
+ // In some cases intrinsics that are a source of divergence have been
+ // lowered to AMDGPUISD so we also need to check those too.
+ case AMDGPUISD::INTERP_MOV:
+ case AMDGPUISD::INTERP_P1:
+ case AMDGPUISD::INTERP_P2:
+ return true;
}
return false;
}
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