diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 19 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 107 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | 23 |
6 files changed, 102 insertions, 68 deletions
diff --git a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp index 0fd593fcfbe..49c42fd1880 100644 --- a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -236,6 +236,7 @@ bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) { // beq $r0, $zero, $L2 => beqz $r0, $L2 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); case Mips::BNE: + case Mips::BNE_MM: // bne $r0, $zero, $L2 => bnez $r0, $L2 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); case Mips::BNE64: diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index f27370f57fa..3e839271a43 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -1047,6 +1047,15 @@ def : MipsPat<(atomic_load_16 addr:$a), def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_MM addr:$src)>; +defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM, + SLTiu_MM, ZERO>; + +defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>; +defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>; +defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>; +defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>; +defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>; + //===----------------------------------------------------------------------===// // MicroMips instruction aliases //===----------------------------------------------------------------------===// @@ -1080,6 +1089,12 @@ let Predicates = [InMicroMips] in { (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : MipsInstAlias<"tne $rs, $rt", (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; + def : MipsInstAlias<"slt $rs, $rt, $imm", + (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, + simm32_relaxed:$imm), 0>; + def : MipsInstAlias<"sltu $rs, $rt, $imm", + (SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, + simm32_relaxed:$imm), 0>; def : MipsInstAlias<"sll $rd, $rt, $rs", (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; def : MipsInstAlias<"sra $rd, $rt, $rs", @@ -1115,4 +1130,8 @@ let Predicates = [InMicroMips] in { (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; def : MipsInstAlias<"not $rt, $rs", (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; + def : MipsInstAlias<"bnez $rs,$offset", + (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; + def : MipsInstAlias<"beqz $rs,$offset", + (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; } diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 88cfec5bc13..c1bffcd497d 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -537,21 +537,21 @@ let AdditionalPredicates = [NotInMicroMips] in { def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>; } -defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, +defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, ZERO_64>; - def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), (BLEZ64 i64:$lhs, bb:$dst)>; def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), (BGEZ64 i64:$lhs, bb:$dst)>; // setcc patterns -defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>; -defm : SetlePats<GPR64, SLT64, SLTu64>; -defm : SetgtPats<GPR64, SLT64, SLTu64>; -defm : SetgePats<GPR64, SLT64, SLTu64>; -defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>; - +let AdditionalPredicates = [NotInMicroMips] in { + defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>; + defm : SetlePats<GPR64, XORi, SLT64, SLTu64>; + defm : SetgtPats<GPR64, SLT64, SLTu64>; + defm : SetgePats<GPR64, XORi, SLT64, SLTu64>; + defm : SetgeImmPats<GPR64, XORi, SLTi64, SLTiu64>; +} // truncate def : MipsPat<(trunc (assertsext GPR64:$src)), (EXTRACT_SUBREG GPR64:$src, sub_32)>; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index 800d834e0ab..9bbdd7db8b8 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -269,7 +269,9 @@ unsigned MipsInstrInfo::getEquivalentCompactForm( if (Subtarget.inMicroMipsMode()) { switch (Opcode) { case Mips::BNE: + case Mips::BNE_MM: case Mips::BEQ: + case Mips::BEQ_MM: // microMIPS has NE,EQ branches that do not have delay slots provided one // of the operands is zero. if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg()) @@ -302,12 +304,14 @@ unsigned MipsInstrInfo::getEquivalentCompactForm( case Mips::BAL: return Mips::BALC; case Mips::BEQ: + case Mips::BEQ_MM: if (canUseShortMicroMipsCTI) return Mips::BEQZC_MM; else if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) return 0; return Mips::BEQC; case Mips::BNE: + case Mips::BNE_MM: if (canUseShortMicroMipsCTI) return Mips::BNEZC_MM; else if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 296f6e9b08b..8bdcb18f719 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1686,33 +1686,35 @@ let AdditionalPredicates = [NotInMicroMips] in { } def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6; -def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, - SLTI_FM<0xa>; -def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, - SLTI_FM<0xb>; +let AdditionalPredicates = [NotInMicroMips] in { + def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, + SLTI_FM<0xa>; + def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, + SLTI_FM<0xb>; +} def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM; let AdditionalPredicates = [NotInMicroMips] in { -/// Arithmetic Instructions (3-Operand, R-Type) -def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, - ADD_FM<0, 0x21>; -def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, - ADD_FM<0, 0x23>; + /// Arithmetic Instructions (3-Operand, R-Type) + def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, + ADD_FM<0, 0x21>; + def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, + ADD_FM<0, 0x23>; } let Defs = [HI0, LO0] in def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, ADD_FM<0, 0x20>; def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, ADD_FM<0, 0x22>; -def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; -def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; let AdditionalPredicates = [NotInMicroMips] in { -def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, - ADD_FM<0, 0x24>; -def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, - ADD_FM<0, 0x25>; -def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, - ADD_FM<0, 0x26>; -def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; + def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; + def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; + def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, + ADD_FM<0, 0x24>; + def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, + ADD_FM<0, 0x25>; + def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, + ADD_FM<0, 0x26>; + def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; } /// Shift Instructions @@ -2223,13 +2225,13 @@ def : MipsInstAlias<"negu $rt", (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>; def : MipsInstAlias<"negu $rt, $rs", (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; -def : MipsInstAlias< +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsInstAlias< "slt $rs, $rt, $imm", (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; -def : MipsInstAlias< + def : MipsInstAlias< "sltu $rt, $rs, $imm", (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; -let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias< "and $rs, $rt, $imm", (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; @@ -2558,38 +2560,39 @@ let AdditionalPredicates = [NotInMicroMips] in { def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; // brcond patterns -multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, - Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, - Instruction SLTiuOp, Register ZEROReg> { +multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BEQOp1, + Instruction BNEOp, Instruction SLTOp, Instruction SLTuOp, + Instruction SLTiOp, Instruction SLTiuOp, + Register ZEROReg> { def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), - (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), - (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), - (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; + (BEQOp1 (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), - (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; + (BEQOp1 (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; def : MipsPat<(brcond RC:$cond, bb:$dst), (BNEOp RC:$cond, ZEROReg, bb:$dst)>; } - -defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; - +let AdditionalPredicates = [NotInMicroMips] in { + defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; +} def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), (BLEZ i32:$lhs, bb:$dst)>; def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), @@ -2608,11 +2611,12 @@ multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; } -multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { +multiclass SetlePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp, + Instruction SLTuOp> { def : MipsPat<(setle RC:$lhs, RC:$rhs), - (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; + (XORiOp (SLTOp RC:$rhs, RC:$lhs), 1)>; def : MipsPat<(setule RC:$lhs, RC:$rhs), - (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; + (XORiOp (SLTuOp RC:$rhs, RC:$lhs), 1)>; } multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { @@ -2622,26 +2626,29 @@ multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { (SLTuOp RC:$rhs, RC:$lhs)>; } -multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { +multiclass SetgePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp, + Instruction SLTuOp> { def : MipsPat<(setge RC:$lhs, RC:$rhs), - (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; + (XORiOp (SLTOp RC:$lhs, RC:$rhs), 1)>; def : MipsPat<(setuge RC:$lhs, RC:$rhs), - (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; + (XORiOp (SLTuOp RC:$lhs, RC:$rhs), 1)>; } -multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, - Instruction SLTiuOp> { +multiclass SetgeImmPats<RegisterClass RC, Instruction XORiOp, + Instruction SLTiOp, Instruction SLTiuOp> { def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), - (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; + (XORiOp (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), - (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; + (XORiOp (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; } -defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; -defm : SetlePats<GPR32, SLT, SLTu>; -defm : SetgtPats<GPR32, SLT, SLTu>; -defm : SetgePats<GPR32, SLT, SLTu>; -defm : SetgeImmPats<GPR32, SLTi, SLTiu>; +let AdditionalPredicates = [NotInMicroMips] in { + defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; + defm : SetlePats<GPR32, XORi, SLT, SLTu>; + defm : SetgtPats<GPR32, SLT, SLTu>; + defm : SetgePats<GPR32, XORi, SLT, SLTu>; + defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>; +} // bswap pattern def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index 29107b2c1aa..4caa3e0c2b2 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -408,7 +408,9 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { switch (Opc) { default: llvm_unreachable("Illegal opcode!"); case Mips::BEQ: return Mips::BNE; + case Mips::BEQ_MM: return Mips::BNE_MM; case Mips::BNE: return Mips::BEQ; + case Mips::BNE_MM: return Mips::BEQ_MM; case Mips::BGTZ: return Mips::BLEZ; case Mips::BGEZ: return Mips::BLTZ; case Mips::BLTZ: return Mips::BGEZ; @@ -506,16 +508,17 @@ unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, } unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { - return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || - Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || - Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || - Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || - Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || - Opc == Mips::J || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || - Opc == Mips::BEQC || Opc == Mips::BNEC || Opc == Mips::BLTC || - Opc == Mips::BGEC || Opc == Mips::BLTUC || Opc == Mips::BGEUC || - Opc == Mips::BGTZC || Opc == Mips::BLEZC || Opc == Mips::BGEZC || - Opc == Mips::BLTZC || Opc == Mips::BEQZC || Opc == Mips::BNEZC || + return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE || + Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ || + Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || + Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || + Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || + Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || + Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || + Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC || + Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC || + Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC || + Opc == Mips::BEQZC || Opc == Mips::BNEZC || Opc == Mips::BC) ? Opc : 0; } |
