diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Analysis/LoopAccessAnalysis.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/IR/LLVMContextImpl.h | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp | 2 | 
5 files changed, 11 insertions, 11 deletions
| diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp index 4ae31627f78..cb0388def5e 100644 --- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp +++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp @@ -1434,7 +1434,7 @@ MemoryDepChecker::getInstructionsForAccess(Value *Ptr, bool isWrite) const {    auto &IndexVector = Accesses.find(Access)->second;    SmallVector<Instruction *, 4> Insts; -  std::transform(IndexVector.begin(), IndexVector.end(), +  transform(IndexVector,                   std::back_inserter(Insts),                   [&](unsigned Idx) { return this->InstMap[Idx]; });    return Insts; @@ -1823,9 +1823,8 @@ static SmallVector<std::pair<PointerBounds, PointerBounds>, 4> expandBounds(    // Here we're relying on the SCEV Expander's cache to only emit code for the    // same bounds once. -  std::transform( -      PointerChecks.begin(), PointerChecks.end(), -      std::back_inserter(ChecksWithBounds), +  transform( +      PointerChecks, std::back_inserter(ChecksWithBounds),        [&](const RuntimePointerChecking::PointerCheck &Check) {          PointerBounds            First = expandBounds(Check.first, L, Loc, Exp, SE, PtrRtChecking), diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp index 2c3292527f5..9bb8b2f50bb 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -2858,7 +2858,7 @@ std::error_code BitcodeReader::resolveGlobalAndIndirectSymbolInits() {  static APInt readWideAPInt(ArrayRef<uint64_t> Vals, unsigned TypeBits) {    SmallVector<uint64_t, 8> Words(Vals.size()); -  std::transform(Vals.begin(), Vals.end(), Words.begin(), +  transform(Vals, Words.begin(),                   BitcodeReader::decodeSignRotatedValue);    return APInt(TypeBits, Words); diff --git a/llvm/lib/IR/LLVMContextImpl.h b/llvm/lib/IR/LLVMContextImpl.h index e808a60aa1b..1d0b1b1524a 100644 --- a/llvm/lib/IR/LLVMContextImpl.h +++ b/llvm/lib/IR/LLVMContextImpl.h @@ -998,7 +998,8 @@ public:    ///    /// Erases all attachments matching the \c shouldRemove predicate.    template <class PredTy> void remove_if(PredTy shouldRemove) { -    Attachments.erase(remove_if(Attachments, shouldRemove), Attachments.end()); +    Attachments.erase(llvm::remove_if(Attachments, shouldRemove), +                      Attachments.end());    }  }; diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 8d649250f65..383b7ca4ddd 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -1266,7 +1266,7 @@ void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,    SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);    if (Narrow) -    std::transform(Regs.begin(), Regs.end(), Regs.begin(), +    transform(Regs, Regs.begin(),                     WidenVector(*CurDAG));    SDValue RegSeq = createQTuple(Regs); @@ -1305,7 +1305,7 @@ void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,    SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);    if (Narrow) -    std::transform(Regs.begin(), Regs.end(), Regs.begin(), +    transform(Regs, Regs.begin(),                     WidenVector(*CurDAG));    SDValue RegSeq = createQTuple(Regs); @@ -1360,7 +1360,7 @@ void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,    SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);    if (Narrow) -    std::transform(Regs.begin(), Regs.end(), Regs.begin(), +    transform(Regs, Regs.begin(),                     WidenVector(*CurDAG));    SDValue RegSeq = createQTuple(Regs); @@ -1390,7 +1390,7 @@ void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,    SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);    if (Narrow) -    std::transform(Regs.begin(), Regs.end(), Regs.begin(), +    transform(Regs, Regs.begin(),                     WidenVector(*CurDAG));    SDValue RegSeq = createQTuple(Regs); diff --git a/llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp b/llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp index 9e3d7e181bb..358253266eb 100644 --- a/llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp +++ b/llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp @@ -347,7 +347,7 @@ public:      // Collect the pointers of the candidate loads.      // FIXME: SmallSet does not work with std::inserter.      std::set<Value *> CandLoadPtrs; -    std::transform(Candidates.begin(), Candidates.end(), +    transform(Candidates,                     std::inserter(CandLoadPtrs, CandLoadPtrs.begin()),                     std::mem_fn(&StoreToLoadForwardingCandidate::getLoadPtr)); | 

