diff options
Diffstat (limited to 'llvm/lib')
4 files changed, 27 insertions, 17 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISD.def b/llvm/lib/Target/WebAssembly/WebAssemblyISD.def index 13f0476eb4a..ba04fd4eb9d 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISD.def +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISD.def @@ -30,9 +30,9 @@ HANDLE_NODETYPE(SWIZZLE) HANDLE_NODETYPE(VEC_SHL) HANDLE_NODETYPE(VEC_SHR_S) HANDLE_NODETYPE(VEC_SHR_U) -HANDLE_NODETYPE(LOAD_SPLAT) HANDLE_NODETYPE(THROW) HANDLE_NODETYPE(MEMORY_COPY) HANDLE_NODETYPE(MEMORY_FILL) -// add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here... +// Memory intrinsics +HANDLE_MEM_NODETYPE(LOAD_SPLAT) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index 2f698711a74..5cb796e389f 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -466,11 +466,14 @@ const char * WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const { switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) { case WebAssemblyISD::FIRST_NUMBER: + case WebAssemblyISD::FIRST_MEM_OPCODE: break; #define HANDLE_NODETYPE(NODE) \ case WebAssemblyISD::NODE: \ return "WebAssemblyISD::" #NODE; +#define HANDLE_MEM_NODETYPE(NODE) HANDLE_NODETYPE(NODE) #include "WebAssemblyISD.def" +#undef HANDLE_MEM_NODETYPE #undef HANDLE_NODETYPE } return nullptr; @@ -1432,7 +1435,11 @@ SDValue WebAssemblyTargetLowering::LowerBUILD_VECTOR(SDValue Op, if (Subtarget->hasUnimplementedSIMD128() && (SplattedLoad = dyn_cast<LoadSDNode>(SplatValue)) && SplattedLoad->getMemoryVT() == VecT.getVectorElementType()) { - Result = DAG.getNode(WebAssemblyISD::LOAD_SPLAT, DL, VecT, SplatValue); + Result = DAG.getMemIntrinsicNode( + WebAssemblyISD::LOAD_SPLAT, DL, DAG.getVTList({VecT}), + {SplattedLoad->getChain(), SplattedLoad->getBasePtr(), + SplattedLoad->getOffset()}, + SplattedLoad->getMemoryVT(), SplattedLoad->getMemOperand()); } else { Result = DAG.getSplatBuildVector(VecT, DL, SplatValue); } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h index 90936670c47..58e088a0ba5 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h @@ -24,8 +24,16 @@ namespace WebAssemblyISD { enum NodeType : unsigned { FIRST_NUMBER = ISD::BUILTIN_OP_END, #define HANDLE_NODETYPE(NODE) NODE, +#define HANDLE_MEM_NODETYPE(NODE) #include "WebAssemblyISD.def" + FIRST_MEM_OPCODE = ISD::FIRST_TARGET_MEMORY_OPCODE, #undef HANDLE_NODETYPE +#undef HANDLE_MEM_NODETYPE +#define HANDLE_NODETYPE(NODE) +#define HANDLE_MEM_NODETYPE(NODE) NODE, +#include "WebAssemblyISD.def" +#undef HANDLE_NODETYPE +#undef HANDLE_MEM_NODETYPE }; } // end namespace WebAssemblyISD diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index fc5d73dac52..751c565d37f 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -72,35 +72,30 @@ defm "" : SIMDLoadSplat<"v16x8", 195>; defm "" : SIMDLoadSplat<"v32x4", 196>; defm "" : SIMDLoadSplat<"v64x2", 197>; -def wasm_load_splat_t : SDTypeProfile<1, 1, []>; -def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t>; - -foreach args = [["v16i8", "i32", "extloadi8"], ["v8i16", "i32", "extloadi16"], - ["v4i32", "i32", "load"], ["v2i64", "i64", "load"], - ["v4f32", "f32", "load"], ["v2f64", "f64", "load"]] in -def load_splat_#args[0] : - PatFrag<(ops node:$addr), (wasm_load_splat - (!cast<ValueType>(args[1]) (!cast<PatFrag>(args[2]) node:$addr)))>; +def wasm_load_splat_t : SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>; +def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; +def load_splat : PatFrag<(ops node:$addr), (wasm_load_splat node:$addr)>; let Predicates = [HasUnimplementedSIMD128] in foreach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32", "v32x4"], ["v2i64", "v64x2"], ["v4f32", "v32x4"], ["v2f64", "v64x2"]] in { def : LoadPatNoOffset<!cast<ValueType>(args[0]), - !cast<PatFrag>("load_splat_"#args[0]), + load_splat, !cast<NI>("LOAD_SPLAT_"#args[1])>; def : LoadPatImmOff<!cast<ValueType>(args[0]), - !cast<PatFrag>("load_splat_"#args[0]), + load_splat, regPlusImm, !cast<NI>("LOAD_SPLAT_"#args[1])>; def : LoadPatImmOff<!cast<ValueType>(args[0]), - !cast<PatFrag>("load_splat_"#args[0]), + load_splat, or_is_add, !cast<NI>("LOAD_SPLAT_"#args[1])>; def : LoadPatOffsetOnly<!cast<ValueType>(args[0]), - !cast<PatFrag>("load_splat_"#args[0]), + load_splat, !cast<NI>("LOAD_SPLAT_"#args[1])>; def : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]), - !cast<PatFrag>("load_splat_"#args[0]), + load_splat, !cast<NI>("LOAD_SPLAT_"#args[1])>; } |
