diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFastISel.cpp | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index d89050e370b..d46ed95b1af 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -811,7 +811,15 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, bool needReg0Op = false; switch (VT.getSimpleVT().SimpleTy) { default: return false; - case MVT::i1: + case MVT::i1: { + unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass : + ARM::GPRRegisterClass); + unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri; + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(Opc), Res) + .addReg(SrcReg).addImm(1)); + SrcReg = Res; + } // Fallthrough here. case MVT::i8: StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12; break; @@ -841,7 +849,6 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, if (isFloat) Offset /= 4; - // FIXME: The 'needReg0Op' bit goes away once STRH is converted to // not use the mega-addrmode stuff. if (!needReg0Op) |
