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-rw-r--r--llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp10
-rw-r--r--llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp2
2 files changed, 11 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index ce274c7cf0a..a5f1bafbc21 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -113,6 +113,10 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID,
return AArch64::LSRVWr;
case TargetOpcode::G_ASHR:
return AArch64::ASRVWr;
+ case TargetOpcode::G_SDIV:
+ return AArch64::SDIVWr;
+ case TargetOpcode::G_UDIV:
+ return AArch64::UDIVWr;
default:
return GenericOpc;
}
@@ -134,6 +138,10 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID,
return AArch64::LSRVXr;
case TargetOpcode::G_ASHR:
return AArch64::ASRVXr;
+ case TargetOpcode::G_SDIV:
+ return AArch64::SDIVXr;
+ case TargetOpcode::G_UDIV:
+ return AArch64::UDIVXr;
default:
return GenericOpc;
}
@@ -289,6 +297,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
case TargetOpcode::G_SHL:
case TargetOpcode::G_LSHR:
case TargetOpcode::G_ASHR:
+ case TargetOpcode::G_SDIV:
+ case TargetOpcode::G_UDIV:
case TargetOpcode::G_ADD:
case TargetOpcode::G_SUB: {
// Reject the various things we don't support yet.
diff --git a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
index 989aeb2f951..c04e93f14e6 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
@@ -42,7 +42,7 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
setAction(BinOp, Ty, WidenScalar);
}
- for (auto BinOp : {G_SHL, G_LSHR, G_ASHR})
+ for (auto BinOp : {G_SHL, G_LSHR, G_ASHR, G_SDIV, G_UDIV})
for (auto Ty : {s32, s64})
setAction(BinOp, Ty, Legal);
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