diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 2c8a4183f17..cd02150c0a2 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -475,7 +475,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, // Also, try to fold ADD into CSINC/CSINV.. setTargetDAGCombine(ISD::ADD); setTargetDAGCombine(ISD::SUB); - + setTargetDAGCombine(ISD::SRL); setTargetDAGCombine(ISD::XOR); setTargetDAGCombine(ISD::SINT_TO_FP); setTargetDAGCombine(ISD::UINT_TO_FP); @@ -8001,6 +8001,34 @@ static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, return SDValue(); } +static SDValue performSRLCombine(SDNode *N, + TargetLowering::DAGCombinerInfo &DCI) { + SelectionDAG &DAG = DCI.DAG; + EVT VT = N->getValueType(0); + if (VT != MVT::i32 && VT != MVT::i64) + return SDValue(); + + // Canonicalize (srl (bswap i32 x), 16) to (rotr (bswap i32 x), 16), if the + // high 16-bits of x are zero. Similarly, canonicalize (srl (bswap i64 x), 32) + // to (rotr (bswap i64 x), 32), if the high 32-bits of x are zero. + SDValue N0 = N->getOperand(0); + if (N0.getOpcode() == ISD::BSWAP) { + SDLoc DL(N); + SDValue N1 = N->getOperand(1); + SDValue N00 = N0.getOperand(0); + if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { + uint64_t ShiftAmt = C->getZExtValue(); + if (VT == MVT::i32 && ShiftAmt == 16 && + DAG.MaskedValueIsZero(N00, APInt::getHighBitsSet(32, 16))) + return DAG.getNode(ISD::ROTR, DL, VT, N0, N1); + if (VT == MVT::i64 && ShiftAmt == 32 && + DAG.MaskedValueIsZero(N00, APInt::getHighBitsSet(64, 32))) + return DAG.getNode(ISD::ROTR, DL, VT, N0, N1); + } + } + return SDValue(); +} + static SDValue performBitcastCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) { @@ -9893,6 +9921,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N, return performFDivCombine(N, DAG, Subtarget); case ISD::OR: return performORCombine(N, DCI, Subtarget); + case ISD::SRL: + return performSRLCombine(N, DCI); case ISD::INTRINSIC_WO_CHAIN: return performIntrinsicCombine(N, DCI, Subtarget); case ISD::ANY_EXTEND: |
