diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 4 |
2 files changed, 5 insertions, 8 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 80ad23ba69a..fc9855f6a0d 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -2087,8 +2087,7 @@ static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op, (void)BitWidth; assert(BitWidth == 32 || BitWidth == 64); - KnownBits Known; - CurDAG->computeKnownBits(Op, Known); + KnownBits Known = CurDAG->computeKnownBits(Op); // Non-zero in the sense that they're not provably zero, which is the key // point if we want to use this value @@ -2167,8 +2166,7 @@ static bool tryBitfieldInsertOpFromOrAndImm(SDNode *N, SelectionDAG *CurDAG) { // Compute the Known Zero for the AND as this allows us to catch more general // cases than just looking for AND with imm. - KnownBits Known; - CurDAG->computeKnownBits(And, Known); + KnownBits Known = CurDAG->computeKnownBits(And); // Non-zero in the sense that they're not provably zero, which is the key // point if we want to use this value. @@ -2309,8 +2307,7 @@ static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits, // This allows to catch more general case than just looking for // AND with imm. Indeed, simplify-demanded-bits may have removed // the AND instruction because it proves it was useless. - KnownBits Known; - CurDAG->computeKnownBits(OrOpd1Val, Known); + KnownBits Known = CurDAG->computeKnownBits(OrOpd1Val); // Check if there is enough room for the second operand to appear // in the first one diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index cc10c9688e1..623815e29eb 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -993,8 +993,8 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode( break; case AArch64ISD::CSEL: { KnownBits Known2; - DAG.computeKnownBits(Op->getOperand(0), Known, Depth + 1); - DAG.computeKnownBits(Op->getOperand(1), Known2, Depth + 1); + Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1); + Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1); Known.Zero &= Known2.Zero; Known.One &= Known2.One; break; |

