diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 20 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 31 |
2 files changed, 51 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 8ff5cd2163a..8032f50eef9 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -527,6 +527,26 @@ let Predicates = [HasSVE] in { defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">; defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">; + defm SQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00100, "sqincb">; + defm UQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00101, "uqincb">; + defm SQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00110, "sqdecb">; + defm UQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00111, "uqdecb">; + + defm SQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01100, "sqinch">; + defm UQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01101, "uqinch">; + defm SQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01110, "sqdech">; + defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech">; + + defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw">; + defm UQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10101, "uqincw">; + defm SQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10110, "sqdecw">; + defm UQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10111, "uqdecw">; + + defm SQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11100, "sqincd">; + defm UQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11101, "uqincd">; + defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">; + defm UQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11111, "uqdecd">; + defm INDEX_RR : sve_int_index_rr<"index">; defm INDEX_IR : sve_int_index_ir<"index">; defm INDEX_RI : sve_int_index_ri<"index">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index f4a63bb1a71..d4e41310f9e 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -314,6 +314,37 @@ multiclass sve_int_pred_pattern_a<bits<3> opc, string asm> { (!cast<Instruction>(NAME) GPR64:$Rdn, 0b11111, 1), 2>; } +class sve_int_pred_pattern_b<bits<5> opc, string asm, RegisterOperand dt, + RegisterOperand st> +: I<(outs dt:$Rdn), (ins st:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), + asm, "\t$Rdn, $pattern, mul $imm4", + "", + []>, Sched<[]> { + bits<5> Rdn; + bits<5> pattern; + bits<4> imm4; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = opc{4-3}; + let Inst{21} = 0b1; + let Inst{20} = opc{2}; + let Inst{19-16} = imm4; + let Inst{15-12} = 0b1111; + let Inst{11-10} = opc{1-0}; + let Inst{9-5} = pattern; + let Inst{4-0} = Rdn; + + let Constraints = "$Rdn = $_Rdn"; +} + +multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm> { + def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>; + + def : InstAlias<asm # "\t$Rdn, $pattern", + (!cast<Instruction>(NAME) GPR64z:$Rdn, sve_pred_enum:$pattern, 1), 1>; + def : InstAlias<asm # "\t$Rdn", + (!cast<Instruction>(NAME) GPR64z:$Rdn, 0b11111, 1), 2>; +} + //===----------------------------------------------------------------------===// // SVE Permute - Cross Lane Group |
