diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 32 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 10 |
3 files changed, 38 insertions, 6 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp index 6d7438399fe..7d4aadcc5ca 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp @@ -446,7 +446,7 @@ bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const { bool AMDGPUTargetLowering::isFNegFree(EVT VT) const { assert(VT.isFloatingPoint()); - return VT == MVT::f32; + return VT == MVT::f32 || VT == MVT::f64; } bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const { diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index 508ed2a9a9a..1d5b43f5954 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -223,10 +223,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : setOperationAction(ISD::FRINT, MVT::f64, Legal); } - // FIXME: These should be removed and handled the same was as f32 fneg. Source - // modifiers also work for the double instructions. - setOperationAction(ISD::FNEG, MVT::f64, Expand); - setOperationAction(ISD::FDIV, MVT::f32, Custom); setTargetDAGCombine(ISD::SELECT_CC); @@ -701,6 +697,7 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( unsigned DestReg = MI->getOperand(0).getReg(); unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); + // FIXME: Should use SALU instructions BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg) .addImm(0x80000000); BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), DestReg) @@ -709,6 +706,33 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( MI->eraseFromParent(); break; } + case AMDGPU::FNEG64_SI: { + MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); + const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( + getTargetMachine().getSubtargetImpl()->getInstrInfo()); + + DebugLoc DL = MI->getDebugLoc(); + unsigned SrcReg = MI->getOperand(1).getReg(); + unsigned DestReg = MI->getOperand(0).getReg(); + + unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); + unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); + + // FIXME: Should use SALU instructions + BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), ImmReg) + .addImm(0x80000000); + BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), TmpReg) + .addReg(SrcReg, 0, AMDGPU::sub1) + .addReg(ImmReg); + + BuildMI(*BB, I, DL, TII->get(AMDGPU::REG_SEQUENCE), DestReg) + .addReg(SrcReg, 0, AMDGPU::sub0) + .addImm(AMDGPU::sub0) + .addReg(TmpReg) + .addImm(AMDGPU::sub1); + MI->eraseFromParent(); + break; + } case AMDGPU::FCLAMP_SI: { const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( getTargetMachine().getSubtargetImpl()->getInstrInfo()); diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index af8d3b3d080..8d2c212dc15 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -2328,12 +2328,20 @@ def : Pat < // TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly // removing these patterns - def : Pat < (fneg (fabs f32:$src)), (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */ >; +def : Pat < + (fneg (fabs f64:$src)), + (f64 (INSERT_SUBREG + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), + (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0), + (V_OR_B32_e32 (S_MOV_B32 0x80000000), + (EXTRACT_SUBREG f64:$src, sub1)), sub1)) // Set sign bit. +>; + class SIUnaryCustomInsertInst<string name, SDPatternOperator node, ValueType vt, RegisterClass dstrc, |
