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-rwxr-xr-xllvm/lib/Target/X86/X86SchedBroadwell.td43
-rw-r--r--llvm/lib/Target/X86/X86SchedHaswell.td43
-rw-r--r--llvm/lib/Target/X86/X86SchedSandyBridge.td1
-rw-r--r--llvm/lib/Target/X86/X86SchedSkylakeClient.td20
-rwxr-xr-xllvm/lib/Target/X86/X86SchedSkylakeServer.td19
-rw-r--r--llvm/lib/Target/X86/X86ScheduleAtom.td5
6 files changed, 9 insertions, 122 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index cb366ef38ec..15ffc8fa937 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -951,15 +951,7 @@ def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLDrm",
- "MMX_PSLLQrm",
- "MMX_PSLLWrm",
- "MMX_PSRADrm",
- "MMX_PSRAWrm",
- "MMX_PSRLDrm",
- "MMX_PSRLQrm",
- "MMX_PSRLWrm",
- "VCVTPH2PS(Y?)rm",
+def: InstRW<[BWWriteResGroup59], (instregex "VCVTPH2PS(Y?)rm",
"(V?)CVTPS2PDrm",
"(V?)CVTSS2SDrm",
"VPSLLVQrm",
@@ -983,16 +975,7 @@ def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi",
- "MMX_PINSRWrm",
- "MMX_PSHUFBrm",
- "MMX_PUNPCKHBWirm",
- "MMX_PUNPCKHDQirm",
- "MMX_PUNPCKHWDirm",
- "MMX_PUNPCKLBWirm",
- "MMX_PUNPCKLDQirm",
- "MMX_PUNPCKLWDirm",
- "(V?)INSERTPSrm",
+def: InstRW<[BWWriteResGroup61], (instregex "(V?)INSERTPSrm",
"(V?)MOVHPDrm",
"(V?)MOVHPSrm",
"(V?)MOVLPDrm",
@@ -1057,18 +1040,6 @@ def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
"BLSI(32|64)rm",
"BLSMSK(32|64)rm",
"BLSR(32|64)rm",
- "MMX_PADD(B|D|Q|W)irm",
- "MMX_PADDS(B|W)irm",
- "MMX_PADDUS(B|W)irm",
- "MMX_PAVG(B|W)irm",
- "MMX_PCMPEQ(B|D|W)irm",
- "MMX_PCMPGT(B|D|W)irm",
- "MMX_P(MAX|MIN)SWirm",
- "MMX_P(MAX|MIN)UBirm",
- "MMX_PSIGN(B|D|W)rm",
- "MMX_PSUB(B|D|Q|W)irm",
- "MMX_PSUBS(B|W)irm",
- "MMX_PSUBUS(B|W)irm",
"MOVBE(16|32|64)rm",
"(V?)PABSBrm",
"(V?)PABSDrm",
@@ -1679,15 +1650,7 @@ def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
- "MMX_PMADDWDirm",
- "MMX_PMULHRSWrm",
- "MMX_PMULHUWirm",
- "MMX_PMULHWirm",
- "MMX_PMULLWirm",
- "MMX_PMULUDQirm",
- "MMX_PSADBWirm",
- "(V?)PCMPGTQrm",
+def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm",
"(V?)PHMINPOSUWrm",
"(V?)PMADDUBSWrm",
"(V?)PMADDWDrm",
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index e11e380a3ef..4f09cfeb84c 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -781,15 +781,7 @@ def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLDrm",
- "MMX_PSLLQrm",
- "MMX_PSLLWrm",
- "MMX_PSRADrm",
- "MMX_PSRAWrm",
- "MMX_PSRLDrm",
- "MMX_PSRLQrm",
- "MMX_PSRLWrm",
- "VCVTPH2PSrm",
+def: InstRW<[HWWriteResGroup11], (instregex "VCVTPH2PSrm",
"(V?)CVTPS2PDrm")>;
def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> {
@@ -944,16 +936,7 @@ def HWWriteResGroup13_2 : SchedWriteRes<[HWPort5,HWPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PALIGNRrmi",
- "MMX_PINSRWrm",
- "MMX_PSHUFBrm",
- "MMX_PUNPCKHBWirm",
- "MMX_PUNPCKHDQirm",
- "MMX_PUNPCKHWDirm",
- "MMX_PUNPCKLBWirm",
- "MMX_PUNPCKLDQirm",
- "MMX_PUNPCKLWDirm",
- "(V?)MOVHPDrm",
+def: InstRW<[HWWriteResGroup13_2], (instregex "(V?)MOVHPDrm",
"(V?)MOVHPSrm",
"(V?)MOVLPDrm",
"(V?)MOVLPSrm",
@@ -990,18 +973,6 @@ def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm",
"BLSI(32|64)rm",
"BLSMSK(32|64)rm",
"BLSR(32|64)rm",
- "MMX_PADD(B|D|Q|W)irm",
- "MMX_PADDS(B|W)irm",
- "MMX_PADDUS(B|W)irm",
- "MMX_PAVG(B|W)irm",
- "MMX_PCMPEQ(B|D|W)irm",
- "MMX_PCMPGT(B|D|W)irm",
- "MMX_P(MAX|MIN)SWirm",
- "MMX_P(MAX|MIN)UBirm",
- "MMX_PSIGN(B|D|W)rm",
- "MMX_PSUB(B|D|Q|W)irm",
- "MMX_PSUBS(B|W)irm",
- "MMX_PSUBUS(B|W)irm",
"MOVBE(16|32|64)rm")>;
def HWWriteResGroup16_1 : SchedWriteRes<[HWPort23,HWPort15]> {
@@ -1953,15 +1924,7 @@ def HWWriteResGroup91 : SchedWriteRes<[HWPort0,HWPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMADDUBSWrm",
- "MMX_PMADDWDirm",
- "MMX_PMULHRSWrm",
- "MMX_PMULHUWirm",
- "MMX_PMULHWirm",
- "MMX_PMULLWirm",
- "MMX_PMULUDQirm",
- "MMX_PSADBWirm",
- "(V?)RCPSSm",
+def: InstRW<[HWWriteResGroup91], (instregex "(V?)RCPSSm",
"(V?)RSQRTSSm")>;
def HWWriteResGroup91_1 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index 3d2d495c5f0..d4214b75bd1 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -904,7 +904,6 @@ def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
}
def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABS(B|D|W)rm",
"MMX_PALIGNRrmi",
- "MMX_PSHUFBrm",
"MMX_PSIGN(B|D|W)rm")>;
def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index 8e9108f1967..5b64ccccb17 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -1131,14 +1131,6 @@ def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm",
"MMX_PMAXUBirm",
"MMX_PMINSWirm",
"MMX_PMINUBirm",
- "MMX_PSLLDrm",
- "MMX_PSLLQrm",
- "MMX_PSLLWrm",
- "MMX_PSRADrm",
- "MMX_PSRAWrm",
- "MMX_PSRLDrm",
- "MMX_PSRLQrm",
- "MMX_PSRLWrm",
"MMX_PSUBSBirm",
"MMX_PSUBSWirm",
"MMX_PSUBUSBirm",
@@ -1161,16 +1153,7 @@ def SKLWriteResGroup71 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PALIGNRrmi",
- "MMX_PINSRWrm",
- "MMX_PSHUFBrm",
- "MMX_PUNPCKHBWirm",
- "MMX_PUNPCKHDQirm",
- "MMX_PUNPCKHWDirm",
- "MMX_PUNPCKLBWirm",
- "MMX_PUNPCKLDQirm",
- "MMX_PUNPCKLWDirm",
- "(V?)MOVHPDrm",
+def: InstRW<[SKLWriteResGroup71], (instregex "(V?)MOVHPDrm",
"(V?)MOVHPSrm",
"(V?)MOVLPDrm",
"(V?)MOVLPSrm",
@@ -1578,7 +1561,6 @@ def: InstRW<[SKLWriteResGroup108], (instregex "FCOM32m",
"FCOM64m",
"FCOMP32m",
"FCOMP64m",
- "MMX_PSADBWirm",
"VPACKSSDWYrm",
"VPACKSSWBYrm",
"VPACKUSDWYrm",
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index d6d89f107e6..eeb5d4d6987 100755
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -2260,14 +2260,6 @@ def: InstRW<[SKXWriteResGroup73], (instregex "MMX_PADDSBirm",
"MMX_PMAXUBirm",
"MMX_PMINSWirm",
"MMX_PMINUBirm",
- "MMX_PSLLDrm",
- "MMX_PSLLQrm",
- "MMX_PSLLWrm",
- "MMX_PSRADrm",
- "MMX_PSRAWrm",
- "MMX_PSRLDrm",
- "MMX_PSRLQrm",
- "MMX_PSRLWrm",
"MMX_PSUBSBirm",
"MMX_PSUBSWirm",
"MMX_PSUBUSBirm",
@@ -2308,16 +2300,7 @@ def SKXWriteResGroup75 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PALIGNRrmi",
- "MMX_PINSRWrm",
- "MMX_PSHUFBrm",
- "MMX_PUNPCKHBWirm",
- "MMX_PUNPCKHDQirm",
- "MMX_PUNPCKHWDirm",
- "MMX_PUNPCKLBWirm",
- "MMX_PUNPCKLDQirm",
- "MMX_PUNPCKLWDirm",
- "MOVHPDrm",
+def: InstRW<[SKXWriteResGroup75], (instregex "MOVHPDrm",
"MOVHPSrm",
"MOVLPDrm",
"MOVLPSrm",
diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td
index 19809845fa2..359a2858c1d 100644
--- a/llvm/lib/Target/X86/X86ScheduleAtom.td
+++ b/llvm/lib/Target/X86/X86ScheduleAtom.td
@@ -320,10 +320,7 @@ def : InstRW<[AtomWrite0_1], (instrs FXAM,
def : InstRW<[AtomWrite0_1], (instregex "(ADC|ADD|AND|NEG|NOT|OR|SBB|SUB|XOR)(8|16|32|64)m",
"(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
"MOV(S|Z)X(32|64)rr(8|8_NOREX|16)",
- "LD_F(P)?(16|32|64)?(m|rr)",
- "MMX_PAVG(B|W)irm",
- "MMX_P(MAX|MIN)(UB|SW)irm",
- "MMX_PSIGN(B|D|W)rm")>;
+ "LD_F(P)?(16|32|64)?(m|rr)")>;
def AtomWrite0_3 : SchedWriteRes<[AtomPort0]> {
let Latency = 3;
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