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-rw-r--r--llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp21
-rw-r--r--llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp32
-rw-r--r--llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp6
-rw-r--r--llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp8
-rw-r--r--llvm/lib/Target/ARM/ARMInstructionSelector.cpp6
-rw-r--r--llvm/lib/Target/X86/X86InstructionSelector.cpp5
6 files changed, 61 insertions, 17 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index e911085d0ad..774ea9877a7 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -345,6 +345,16 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
unsigned Res = getOrCreateVReg(LI);
unsigned Addr = getOrCreateVReg(*LI.getPointerOperand());
+ if (LI.getOrdering() != AtomicOrdering::NotAtomic) {
+ MIRBuilder.buildAtomicLoad(
+ Res, Addr,
+ *MF->getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()),
+ Flags, DL->getTypeStoreSize(LI.getType()),
+ getMemOpAlignment(LI), AAMDNodes(), nullptr,
+ LI.getSyncScopeID(), LI.getOrdering()));
+ return true;
+ }
+
MIRBuilder.buildLoad(
Res, Addr,
*MF->getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()),
@@ -366,6 +376,17 @@ bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
unsigned Val = getOrCreateVReg(*SI.getValueOperand());
unsigned Addr = getOrCreateVReg(*SI.getPointerOperand());
+ if (SI.getOrdering() != AtomicOrdering::NotAtomic) {
+ MIRBuilder.buildAtomicStore(
+ Val, Addr,
+ *MF->getMachineMemOperand(
+ MachinePointerInfo(SI.getPointerOperand()), Flags,
+ DL->getTypeStoreSize(SI.getValueOperand()->getType()),
+ getMemOpAlignment(SI), AAMDNodes(), nullptr, SI.getSyncScopeID(),
+ SI.getOrdering()));
+ return true;
+ }
+
MIRBuilder.buildStore(
Val, Addr,
*MF->getMachineMemOperand(
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 62c396e6cdf..fbcb14d5252 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -295,6 +295,8 @@ MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
MachineMemOperand &MMO) {
assert(MRI->getType(Res).isValid() && "invalid operand type");
assert(MRI->getType(Addr).isPointer() && "invalid operand type");
+ assert(MMO.getOrdering() == AtomicOrdering::NotAtomic &&
+ "invalid atomic ordering");
return buildInstr(TargetOpcode::G_LOAD)
.addDef(Res)
@@ -306,6 +308,8 @@ MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
MachineMemOperand &MMO) {
assert(MRI->getType(Val).isValid() && "invalid operand type");
assert(MRI->getType(Addr).isPointer() && "invalid operand type");
+ assert(MMO.getOrdering() == AtomicOrdering::NotAtomic &&
+ "invalid atomic ordering");
return buildInstr(TargetOpcode::G_STORE)
.addUse(Val)
@@ -313,6 +317,34 @@ MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
.addMemOperand(&MMO);
}
+MachineInstrBuilder MachineIRBuilder::buildAtomicLoad(unsigned Res,
+ unsigned Addr,
+ MachineMemOperand &MMO) {
+ assert(MRI->getType(Res).isValid() && "invalid operand type");
+ assert(MRI->getType(Addr).isPointer() && "invalid operand type");
+ assert(MMO.getOrdering() != AtomicOrdering::NotAtomic &&
+ "invalid atomic ordering");
+
+ return buildInstr(TargetOpcode::G_ATOMIC_LOAD)
+ .addDef(Res)
+ .addUse(Addr)
+ .addMemOperand(&MMO);
+}
+
+MachineInstrBuilder MachineIRBuilder::buildAtomicStore(unsigned Val,
+ unsigned Addr,
+ MachineMemOperand &MMO) {
+ assert(MRI->getType(Val).isValid() && "invalid operand type");
+ assert(MRI->getType(Addr).isPointer() && "invalid operand type");
+ assert(MMO.getOrdering() != AtomicOrdering::NotAtomic &&
+ "invalid atomic ordering");
+
+ return buildInstr(TargetOpcode::G_ATOMIC_STORE)
+ .addUse(Val)
+ .addUse(Addr)
+ .addMemOperand(&MMO);
+}
+
MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res,
unsigned CarryOut,
unsigned Op0, unsigned Op1,
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index c2d3ae31c62..6999721b626 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -889,12 +889,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
return false;
}
- auto &MemOp = **I.memoperands_begin();
- if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
- DEBUG(dbgs() << "Atomic load/store not supported yet\n");
- return false;
- }
-
const unsigned PtrReg = I.getOperand(1).getReg();
#ifndef NDEBUG
const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
index 05df5120222..6531d5ebe4c 100644
--- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -231,6 +231,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
setAction({MemOp, 1, p0}, Legal);
}
+ for (unsigned MemOp : {G_ATOMIC_LOAD, G_ATOMIC_STORE}) {
+ for (auto Ty : {s8, s16, s32, s64, p0})
+ setAction({MemOp, Ty}, Legal);
+
+ // And everything's fine in addrspace 0.
+ setAction({MemOp, 1, p0}, Legal);
+ }
+
// Constants
for (auto Ty : {s32, s64}) {
setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
index 6bbeae2e115..b43faf4903a 100644
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -801,12 +801,6 @@ bool ARMInstructionSelector::select(MachineInstr &I,
return selectGlobal(MIB, MRI);
case G_STORE:
case G_LOAD: {
- const auto &MemOp = **I.memoperands_begin();
- if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
- DEBUG(dbgs() << "Atomic load/store not supported yet\n");
- return false;
- }
-
unsigned Reg = I.getOperand(0).getReg();
unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID();
diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp
index 44bbc3f1b3f..f6530c4eee2 100644
--- a/llvm/lib/Target/X86/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp
@@ -484,11 +484,6 @@ bool X86InstructionSelector::selectLoadStoreOp(MachineInstr &I,
const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
auto &MemOp = **I.memoperands_begin();
- if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
- DEBUG(dbgs() << "Atomic load/store not supported yet\n");
- return false;
- }
-
unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlignment());
if (NewOpc == Opc)
return false;
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