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-rw-r--r--llvm/lib/IR/Function.cpp5
-rw-r--r--llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td4
-rw-r--r--llvm/lib/Target/AArch64/SVEInstrFormats.td13
3 files changed, 18 insertions, 4 deletions
diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp
index a4632762c20..5c22109ffd5 100644
--- a/llvm/lib/IR/Function.cpp
+++ b/llvm/lib/IR/Function.cpp
@@ -1211,8 +1211,9 @@ static bool matchIntrinsicType(
}
case IITDescriptor::HalfVecArgument:
// If this is a forward reference, defer the check for later.
- return D.getArgumentNumber() >= ArgTys.size() ||
- !isa<VectorType>(ArgTys[D.getArgumentNumber()]) ||
+ if (D.getArgumentNumber() >= ArgTys.size())
+ return IsDeferredCheck || DeferCheck(Ty);
+ return !isa<VectorType>(ArgTys[D.getArgumentNumber()]) ||
VectorType::getHalfElementsVectorType(
cast<VectorType>(ArgTys[D.getArgumentNumber()])) != Ty;
case IITDescriptor::SameVecWidthArgument: {
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 0813c41dc66..cdf313db1b9 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -216,8 +216,8 @@ let Predicates = [HasSVE] in {
defm UUNPKLO_ZZ : sve_int_perm_unpk<0b10, "uunpklo">;
defm UUNPKHI_ZZ : sve_int_perm_unpk<0b11, "uunpkhi">;
- def PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo">;
- def PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi">;
+ defm PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo", int_aarch64_sve_punpklo>;
+ defm PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi", int_aarch64_sve_punpkhi>;
defm MOVPRFX_ZPzZ : sve_int_movprfx_pred_zero<0b000, "movprfx">;
defm MOVPRFX_ZPmZ : sve_int_movprfx_pred_merge<0b001, "movprfx">;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 8c8713b464e..f57e111b7e1 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -283,6 +283,11 @@ let Predicates = [HasSVE] in {
// SVE pattern match helpers.
//===----------------------------------------------------------------------===//
+class SVE_1_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
+ Instruction inst>
+: Pat<(vtd (op vt1:$Op1)),
+ (inst $Op1)>;
+
class SVE_3_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
ValueType vt2, ValueType vt3, Instruction inst>
: Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)),
@@ -4280,6 +4285,14 @@ class sve_int_perm_punpk<bit opc, string asm>
let Inst{3-0} = Pd;
}
+multiclass sve_int_perm_punpk<bit opc, string asm, SDPatternOperator op> {
+ def NAME : sve_int_perm_punpk<opc, asm>;
+
+ def : SVE_1_Op_Pat<nxv8i1, op, nxv16i1, !cast<Instruction>(NAME)>;
+ def : SVE_1_Op_Pat<nxv4i1, op, nxv8i1, !cast<Instruction>(NAME)>;
+ def : SVE_1_Op_Pat<nxv2i1, op, nxv4i1, !cast<Instruction>(NAME)>;
+}
+
class sve_int_rdffr_pred<bit s, string asm>
: I<(outs PPR8:$Pd), (ins PPRAny:$Pg),
asm, "\t$Pd, $Pg/z",
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