diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 559a4e8435c..2f836a60a9e 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -5421,7 +5421,12 @@ SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const { // FIXME: Remove this when we have strict fp instruction selection patterns if (IsStrict) { - DAG.mutateStrictFPToFP(Op.getNode()); + SDLoc Loc(Op); + SDValue Result = + DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT + : ISD::FP_TO_UINT, + Loc, Op.getValueType(), SrcVal); + return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc); } return Op; @@ -16384,7 +16389,10 @@ SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const { if (SrcSz == 32 && DstSz == 64 && Subtarget->hasFP64()) { // FIXME: Remove this when we have strict fp instruction selection patterns if (IsStrict) { - DAG.mutateStrictFPToFP(Op.getNode()); + SDLoc Loc(Op); + SDValue Result = DAG.getNode(ISD::FP_EXTEND, + Loc, Op.getValueType(), SrcVal); + return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc); } return Op; } |
