diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 25 |
4 files changed, 18 insertions, 11 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index c0975795604..1751b04800c 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -420,6 +420,7 @@ def : InstAlias<"wfi", (HINT 0b011)>; def : InstAlias<"sev", (HINT 0b100)>; def : InstAlias<"sevl", (HINT 0b101)>; def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>; +def : InstAlias<"csdb", (HINT 20)>; // v8.2a Statistical Profiling extension def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>; diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index e477d16923d..2269e81d713 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -2004,6 +2004,7 @@ def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; +def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>; def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", "\t$Rd, $Rn, $Rm", diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 8ca11d83dcf..249445cccce 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -3700,6 +3700,8 @@ def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> { def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> { let Predicates = [IsThumb2, HasRAS]; } +def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>; +def : t2InstAlias<"csdb$p", (t2HINT 20, pred:$p), 1>; def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", [(int_arm_dbg imm0_15:$opt)]> { diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 55a73ff537c..3d251887883 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -6616,19 +6616,22 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst, break; } case ARM::HINT: - case ARM::t2HINT: - if (hasRAS()) { - // ESB is not predicable (pred must be AL) - unsigned Imm8 = Inst.getOperand(0).getImm(); - unsigned Pred = Inst.getOperand(1).getImm(); - if (Imm8 == 0x10 && Pred != ARMCC::AL) - return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not " - "predicable, but condition " - "code specified"); - } - // Without the RAS extension, this behaves as any other unallocated hint. + case ARM::t2HINT: { + unsigned Imm8 = Inst.getOperand(0).getImm(); + unsigned Pred = Inst.getOperand(1).getImm(); + // ESB is not predicable (pred must be AL). Without the RAS extension, this + // behaves as any other unallocated hint. + if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS()) + return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not " + "predicable, but condition " + "code specified"); + if (Imm8 == 0x14 && Pred != ARMCC::AL) + return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not " + "predicable, but condition " + "code specified"); break; } + } return false; } |
