diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 66 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 52 |
3 files changed, 85 insertions, 40 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 8e3a524ed2c..4a5d3bc4dfd 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -183,6 +183,13 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, addRegisterClass(MVT::nxv4f32, &AArch64::ZPRRegClass); addRegisterClass(MVT::nxv1f64, &AArch64::ZPRRegClass); addRegisterClass(MVT::nxv2f64, &AArch64::ZPRRegClass); + + for (auto VT : { MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64 }) { + setOperationAction(ISD::SADDSAT, VT, Legal); + setOperationAction(ISD::UADDSAT, VT, Legal); + setOperationAction(ISD::SSUBSAT, VT, Legal); + setOperationAction(ISD::USUBSAT, VT, Legal); + } } // Compute derived properties from the register classes diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 502de477f43..4c8d7023c6d 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -18,26 +18,26 @@ let Predicates = [HasSVE] in { def SETFFR : sve_int_setffr<"setffr">; def WRFFR : sve_int_wrffr<"wrffr">; - defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">; - defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">; - defm SQADD_ZZZ : sve_int_bin_cons_arit_0<0b100, "sqadd">; - defm UQADD_ZZZ : sve_int_bin_cons_arit_0<0b101, "uqadd">; - defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub">; - defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub">; - - defm AND_ZZZ : sve_int_bin_cons_log<0b00, "and">; - defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">; - defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">; - defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">; - - defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">; - defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">; - defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr">; - - defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr">; - defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor">; - defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and">; - defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic">; + defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add", add>; + defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub", sub>; + defm SQADD_ZZZ : sve_int_bin_cons_arit_0<0b100, "sqadd", saddsat>; + defm UQADD_ZZZ : sve_int_bin_cons_arit_0<0b101, "uqadd", uaddsat>; + defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub", ssubsat>; + defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub", usubsat>; + + defm AND_ZZZ : sve_int_bin_cons_log<0b00, "and", and>; + defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr", or>; + defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor", xor>; + defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic", int_aarch64_sve_bic>; + + defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add", int_aarch64_sve_add>; + defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub", int_aarch64_sve_sub>; + defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr", int_aarch64_sve_subr>; + + defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr", null_frag>; + defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor", null_frag>; + defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and", null_frag>; + defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic", null_frag>; defm ADD_ZI : sve_int_arith_imm0<0b000, "add">; defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">; @@ -73,14 +73,14 @@ let Predicates = [HasSVE] in { defm UMIN_ZI : sve_int_arith_imm1<0b11, "umin", imm0_255>; defm MUL_ZI : sve_int_arith_imm2<"mul">; - defm MUL_ZPmZ : sve_int_bin_pred_arit_2<0b000, "mul">; - defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh">; - defm UMULH_ZPmZ : sve_int_bin_pred_arit_2<0b011, "umulh">; + defm MUL_ZPmZ : sve_int_bin_pred_arit_2<0b000, "mul", null_frag>; + defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh", null_frag>; + defm UMULH_ZPmZ : sve_int_bin_pred_arit_2<0b011, "umulh", null_frag>; - defm SDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b100, "sdiv">; - defm UDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b101, "udiv">; - defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr">; - defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr">; + defm SDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b100, "sdiv", null_frag>; + defm UDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b101, "udiv", null_frag>; + defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr", null_frag>; + defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr", null_frag>; defm SDOT_ZZZ : sve_intx_dot<0b0, "sdot", int_aarch64_sve_sdot>; defm UDOT_ZZZ : sve_intx_dot<0b1, "udot", int_aarch64_sve_udot>; @@ -105,12 +105,12 @@ let Predicates = [HasSVE] in { defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs">; defm FNEG_ZPmZ : sve_int_un_pred_arit_1_fp<0b101, "fneg">; - defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax">; - defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax">; - defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin">; - defm UMIN_ZPmZ : sve_int_bin_pred_arit_1<0b011, "umin">; - defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd">; - defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd">; + defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax", null_frag>; + defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax", null_frag>; + defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin", null_frag>; + defm UMIN_ZPmZ : sve_int_bin_pred_arit_1<0b011, "umin", null_frag>; + defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd", null_frag>; + defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd", null_frag>; defm FRECPE_ZZ : sve_fp_2op_u_zd<0b110, "frecpe">; defm FRSQRTE_ZZ : sve_fp_2op_u_zd<0b111, "frsqrte">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 12fdb5c102a..583e1430e72 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -288,6 +288,11 @@ class SVE_1_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1, : Pat<(vtd (op vt1:$Op1)), (inst $Op1)>; +class SVE_2_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1, + ValueType vt2, Instruction inst> +: Pat<(vtd (op vt1:$Op1, vt2:$Op2)), + (inst $Op1, $Op2)>; + class SVE_3_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1, ValueType vt2, ValueType vt3, Instruction inst> : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)), @@ -1122,11 +1127,16 @@ class sve_int_bin_cons_arit_0<bits<2> sz8_64, bits<3> opc, string asm, let Inst{4-0} = Zd; } -multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> { +multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm, SDPatternOperator op> { def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>; def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>; def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>; def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>; + + def : SVE_2_Op_Pat<nxv16i8, op, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>; + def : SVE_2_Op_Pat<nxv8i16, op, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>; + def : SVE_2_Op_Pat<nxv4i32, op, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>; + def : SVE_2_Op_Pat<nxv2i64, op, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>; } //===----------------------------------------------------------------------===// @@ -1801,38 +1811,61 @@ class sve_int_bin_pred_arit_log<bits<2> sz8_64, bits<2> fmt, bits<3> opc, let ElementSize = zprty.ElementSize; } -multiclass sve_int_bin_pred_log<bits<3> opc, string asm> { +multiclass sve_int_bin_pred_log<bits<3> opc, string asm, SDPatternOperator op> { def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>; def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>; def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>; def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>; + + def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>; + def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>; + def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>; + def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>; } -multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> { +multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm, SDPatternOperator op> { def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>; def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>; def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>; def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>; + + def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>; + def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>; + def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>; + def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>; } -multiclass sve_int_bin_pred_arit_1<bits<3> opc, string asm> { +multiclass sve_int_bin_pred_arit_1<bits<3> opc, string asm, SDPatternOperator op> { def _B : sve_int_bin_pred_arit_log<0b00, 0b01, opc, asm, ZPR8>; def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, ZPR16>; def _S : sve_int_bin_pred_arit_log<0b10, 0b01, opc, asm, ZPR32>; def _D : sve_int_bin_pred_arit_log<0b11, 0b01, opc, asm, ZPR64>; + + def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>; + def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>; + def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>; + def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>; } -multiclass sve_int_bin_pred_arit_2<bits<3> opc, string asm> { +multiclass sve_int_bin_pred_arit_2<bits<3> opc, string asm, SDPatternOperator op> { def _B : sve_int_bin_pred_arit_log<0b00, 0b10, opc, asm, ZPR8>; def _H : sve_int_bin_pred_arit_log<0b01, 0b10, opc, asm, ZPR16>; def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>; def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>; + + def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>; + def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>; + def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>; + def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>; } // Special case for divides which are not defined for 8b/16b elements. -multiclass sve_int_bin_pred_arit_2_div<bits<3> opc, string asm> { +multiclass sve_int_bin_pred_arit_2_div<bits<3> opc, string asm, SDPatternOperator op> { def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>; def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>; + + def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>; + def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>; } //===----------------------------------------------------------------------===// @@ -3086,9 +3119,14 @@ class sve_int_bin_cons_log<bits<2> opc, string asm> let Inst{4-0} = Zd; } -multiclass sve_int_bin_cons_log<bits<2> opc, string asm> { +multiclass sve_int_bin_cons_log<bits<2> opc, string asm, SDPatternOperator op> { def NAME : sve_int_bin_cons_log<opc, asm>; + def : SVE_2_Op_Pat<nxv16i8, op, nxv16i8, nxv16i8, !cast<Instruction>(NAME)>; + def : SVE_2_Op_Pat<nxv8i16, op, nxv8i16, nxv8i16, !cast<Instruction>(NAME)>; + def : SVE_2_Op_Pat<nxv4i32, op, nxv4i32, nxv4i32, !cast<Instruction>(NAME)>; + def : SVE_2_Op_Pat<nxv2i64, op, nxv2i64, nxv2i64, !cast<Instruction>(NAME)>; + def : InstAlias<asm # "\t$Zd, $Zn, $Zm", (!cast<Instruction>(NAME) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 1>; def : InstAlias<asm # "\t$Zd, $Zn, $Zm", |
