diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeClient.td | 12 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 12 |
3 files changed, 6 insertions, 30 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index b9f9c8c485a..52fc47398e2 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -726,16 +726,12 @@ def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8", "BTR(16|32|64)rr", "BTS(16|32|64)ri8", "BTS(16|32|64)rr", - "RORX(32|64)ri", "SAR(8|16|32|64)r1", "SAR(8|16|32|64)ri", - "SARX(32|64)rr", "SHL(8|16|32|64)r1", "SHL(8|16|32|64)ri", - "SHLX(32|64)rr", "SHR(8|16|32|64)r1", - "SHR(8|16|32|64)ri", - "SHRX(32|64)rr")>; + "SHR(8|16|32|64)ri")>; def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> { let Latency = 1; @@ -956,11 +952,7 @@ def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort06]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8", - "RORX(32|64)mi", - "SARX(32|64)rm", - "SHLX(32|64)rm", - "SHRX(32|64)rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8")>; def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> { let Latency = 6; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 02c8bd83013..8939f01f065 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -463,19 +463,15 @@ def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri", "BTR(16|32|64)rr", "BTS(16|32|64)ri8", "BTS(16|32|64)rr", - "RORX(32|64)ri", "SAR(8|16|32|64)r1", "SAR(8|16|32|64)ri", - "SARX(32|64)rr", "SBB(16|32|64)ri", "SBB(16|32|64)i", "SBB(8|16|32|64)rr", "SHL(8|16|32|64)r1", "SHL(8|16|32|64)ri", - "SHLX(32|64)rr", "SHR(8|16|32|64)r1", - "SHR(8|16|32|64)ri", - "SHRX(32|64)rr")>; + "SHR(8|16|32|64)ri")>; def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> { let Latency = 1; @@ -1185,11 +1181,7 @@ def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8", - "RORX(32|64)mi", - "SARX(32|64)rm", - "SHLX(32|64)rm", - "SHRX(32|64)rm")>; +def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>; def: InstRW<[SKLWriteResGroup74, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm, ADCX32rm, ADCX64rm, ADOX32rm, ADOX64rm, diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 21632fcdaff..5f572b26c72 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -768,19 +768,15 @@ def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri", "BTR(16|32|64)rr", "BTS(16|32|64)ri8", "BTS(16|32|64)rr", - "RORX(32|64)ri", "SAR(8|16|32|64)r1", "SAR(8|16|32|64)ri", - "SARX(32|64)rr", "SBB(16|32|64)ri", "SBB(16|32|64)i", "SBB(8|16|32|64)rr", "SHL(8|16|32|64)r1", "SHL(8|16|32|64)ri", - "SHLX(32|64)rr", "SHR(8|16|32|64)r1", - "SHR(8|16|32|64)ri", - "SHRX(32|64)rr")>; + "SHR(8|16|32|64)ri")>; def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> { let Latency = 1; @@ -2348,11 +2344,7 @@ def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8", - "RORX(32|64)mi", - "SARX(32|64)rm", - "SHLX(32|64)rm", - "SHRX(32|64)rm")>; +def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8")>; def: InstRW<[SKXWriteResGroup78, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm, ADCX32rm, ADCX64rm, ADOX32rm, ADOX64rm, |
