diff options
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | 4 | ||||
-rw-r--r-- | llvm/lib/Target/X86/X86FloatingPoint.cpp | 3 |
2 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp index 2dc6f2702b3..e77c98a72cf 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp @@ -246,6 +246,7 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst); PrepareExecInst->getOperand(0).setReg(AMDGPU::EXEC); + PrepareExecInst->getOperand(0).setIsRenamable(false); DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n'); @@ -352,7 +353,8 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { for (MachineInstr *OtherInst : OtherUseInsts) { OtherInst->substituteRegister(CopyToExec, AMDGPU::EXEC, - AMDGPU::NoSubRegister, *TRI); + AMDGPU::NoSubRegister, *TRI, + /*ClearIsRenamable=*/true); } } diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp index 9a72e7114be..6a13367e3ce 100644 --- a/llvm/lib/Target/X86/X86FloatingPoint.cpp +++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp @@ -1383,6 +1383,7 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { // Change from the pseudo instruction to the concrete instruction. MI.getOperand(0).setReg(getSTReg(Op1)); + MI.getOperand(0).setIsRenamable(false); MI.RemoveOperand(1); MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); @@ -1410,6 +1411,7 @@ void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { MI.RemoveOperand(0); MI.RemoveOperand(1); MI.getOperand(0).setReg(getSTReg(Op1)); + MI.getOperand(0).setIsRenamable(false); MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); // If we kill the second operand, make sure to pop it from the stack. @@ -1626,6 +1628,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) { else // Operand with a single register class constraint ("t" or "u"). Op.setReg(X86::ST0 + FPReg); + Op.setIsRenamable(false); } // Simulate the inline asm popping its inputs and pushing its outputs. |