diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeClient.td | 30 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 42 |
2 files changed, 54 insertions, 18 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index b4d5f880434..d001b0c7181 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -2416,13 +2416,10 @@ def SKLWriteResGroup105 : SchedWriteRes<[SKLPort015]> { let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[SKLWriteResGroup105], (instregex "PMULLDrr")>; def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDPDr")>; def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDPSr")>; def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDSDr")>; def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDSSr")>; -def: InstRW<[SKLWriteResGroup105], (instregex "VPMULLDYrr")>; -def: InstRW<[SKLWriteResGroup105], (instregex "VPMULLDrr")>; def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDPDr")>; def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDPSr")>; def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDSDr")>; @@ -2430,6 +2427,15 @@ def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDSSr")>; def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDYPDr")>; def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDYPSr")>; +def SKLWriteResGroup105_2 : SchedWriteRes<[SKLPort01]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKLWriteResGroup105_2], (instregex "PMULLDrr")>; +def: InstRW<[SKLWriteResGroup105_2], (instregex "VPMULLDYrr")>; +def: InstRW<[SKLWriteResGroup105_2], (instregex "VPMULLDrr")>; + def SKLWriteResGroup106 : SchedWriteRes<[SKLPort0,SKLPort23]> { let Latency = 8; let NumMicroOps = 2; @@ -3278,17 +3284,23 @@ def SKLWriteResGroup168 : SchedWriteRes<[SKLPort23,SKLPort015]> { let NumMicroOps = 3; let ResourceCycles = [1,2]; } -def: InstRW<[SKLWriteResGroup168], (instregex "PMULLDrm")>; def: InstRW<[SKLWriteResGroup168], (instregex "ROUNDPDm")>; def: InstRW<[SKLWriteResGroup168], (instregex "ROUNDPSm")>; def: InstRW<[SKLWriteResGroup168], (instregex "ROUNDSDm")>; def: InstRW<[SKLWriteResGroup168], (instregex "ROUNDSSm")>; -def: InstRW<[SKLWriteResGroup168], (instregex "VPMULLDrm")>; def: InstRW<[SKLWriteResGroup168], (instregex "VROUNDPDm")>; def: InstRW<[SKLWriteResGroup168], (instregex "VROUNDPSm")>; def: InstRW<[SKLWriteResGroup168], (instregex "VROUNDSDm")>; def: InstRW<[SKLWriteResGroup168], (instregex "VROUNDSSm")>; +def SKLWriteResGroup168_2 : SchedWriteRes<[SKLPort23,SKLPort01]> { + let Latency = 16; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKLWriteResGroup168_2], (instregex "PMULLDrm")>; +def: InstRW<[SKLWriteResGroup168_2], (instregex "VPMULLDrm")>; + def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { let Latency = 14; let NumMicroOps = 3; @@ -3318,10 +3330,16 @@ def SKLWriteResGroup172 : SchedWriteRes<[SKLPort23,SKLPort015]> { let NumMicroOps = 3; let ResourceCycles = [1,2]; } -def: InstRW<[SKLWriteResGroup172], (instregex "VPMULLDYrm")>; def: InstRW<[SKLWriteResGroup172], (instregex "VROUNDYPDm")>; def: InstRW<[SKLWriteResGroup172], (instregex "VROUNDYPSm")>; +def SKLWriteResGroup172_2 : SchedWriteRes<[SKLPort23,SKLPort01]> { + let Latency = 17; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKLWriteResGroup172_2], (instregex "VPMULLDYrm")>; + def SKLWriteResGroup173 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> { let Latency = 15; let NumMicroOps = 4; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 695568194bf..c567cff0e5e 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -3869,16 +3869,10 @@ def SKXWriteResGroup116 : SchedWriteRes<[SKXPort015]> { let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[SKXWriteResGroup116], (instregex "PMULLDrr")>; def: InstRW<[SKXWriteResGroup116], (instregex "ROUNDPDr")>; def: InstRW<[SKXWriteResGroup116], (instregex "ROUNDPSr")>; def: InstRW<[SKXWriteResGroup116], (instregex "ROUNDSDr")>; def: InstRW<[SKXWriteResGroup116], (instregex "ROUNDSSr")>; -def: InstRW<[SKXWriteResGroup116], (instregex "VPMULLDYrr")>; -def: InstRW<[SKXWriteResGroup116], (instregex "VPMULLDZ128rr(b?)(k?)(z?)")>; -def: InstRW<[SKXWriteResGroup116], (instregex "VPMULLDZ256rr(b?)(k?)(z?)")>; -def: InstRW<[SKXWriteResGroup116], (instregex "VPMULLDZrr(b?)(k?)(z?)")>; -def: InstRW<[SKXWriteResGroup116], (instregex "VPMULLDrr")>; def: InstRW<[SKXWriteResGroup116], (instregex "VRNDSCALEPDZ128rri(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup116], (instregex "VRNDSCALEPDZ256rri(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup116], (instregex "VRNDSCALEPDZrri(b?)(k?)(z?)")>; @@ -3894,6 +3888,18 @@ def: InstRW<[SKXWriteResGroup116], (instregex "VROUNDSSr")>; def: InstRW<[SKXWriteResGroup116], (instregex "VROUNDYPDr")>; def: InstRW<[SKXWriteResGroup116], (instregex "VROUNDYPSr")>; +def SKXWriteResGroup116_2 : SchedWriteRes<[SKXPort015]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup116_2], (instregex "PMULLDrr")>; +def: InstRW<[SKXWriteResGroup116_2], (instregex "VPMULLDYrr")>; +def: InstRW<[SKXWriteResGroup116_2], (instregex "VPMULLDZ128rr(b?)(k?)(z?)")>; +def: InstRW<[SKXWriteResGroup116_2], (instregex "VPMULLDZ256rr(b?)(k?)(z?)")>; +def: InstRW<[SKXWriteResGroup116_2], (instregex "VPMULLDZrr(b?)(k?)(z?)")>; +def: InstRW<[SKXWriteResGroup116_2], (instregex "VPMULLDrr")>; + def SKXWriteResGroup117 : SchedWriteRes<[SKXPort0,SKXPort23]> { let Latency = 8; let NumMicroOps = 2; @@ -5541,13 +5547,10 @@ def SKXWriteResGroup186 : SchedWriteRes<[SKXPort23,SKXPort015]> { let NumMicroOps = 3; let ResourceCycles = [1,2]; } -def: InstRW<[SKXWriteResGroup186], (instregex "PMULLDrm")>; def: InstRW<[SKXWriteResGroup186], (instregex "ROUNDPDm")>; def: InstRW<[SKXWriteResGroup186], (instregex "ROUNDPSm")>; def: InstRW<[SKXWriteResGroup186], (instregex "ROUNDSDm")>; def: InstRW<[SKXWriteResGroup186], (instregex "ROUNDSSm")>; -def: InstRW<[SKXWriteResGroup186], (instregex "VPMULLDZ128rm(b?)(k?)(z?)")>; -def: InstRW<[SKXWriteResGroup186], (instregex "VPMULLDrm")>; def: InstRW<[SKXWriteResGroup186], (instregex "VRNDSCALEPDZ128rm(b?)i(k?)(z?)")>; def: InstRW<[SKXWriteResGroup186], (instregex "VRNDSCALEPSZ128rm(b?)i(k?)(z?)")>; def: InstRW<[SKXWriteResGroup186], (instregex "VRNDSCALESDm(b?)(k?)(z?)")>; @@ -5557,6 +5560,15 @@ def: InstRW<[SKXWriteResGroup186], (instregex "VROUNDPSm")>; def: InstRW<[SKXWriteResGroup186], (instregex "VROUNDSDm")>; def: InstRW<[SKXWriteResGroup186], (instregex "VROUNDSSm")>; +def SKXWriteResGroup186_2 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 16; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup186_2], (instregex "PMULLDrm")>; +def: InstRW<[SKXWriteResGroup186_2], (instregex "VPMULLDZ128rm(b?)(k?)(z?)")>; +def: InstRW<[SKXWriteResGroup186_2], (instregex "VPMULLDrm")>; + def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { let Latency = 14; let NumMicroOps = 3; @@ -5609,9 +5621,6 @@ def SKXWriteResGroup192 : SchedWriteRes<[SKXPort23,SKXPort015]> { let NumMicroOps = 3; let ResourceCycles = [1,2]; } -def: InstRW<[SKXWriteResGroup192], (instregex "VPMULLDYrm")>; -def: InstRW<[SKXWriteResGroup192], (instregex "VPMULLDZ256rm(b?)(k?)(z?)")>; -def: InstRW<[SKXWriteResGroup192], (instregex "VPMULLDZrm(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup192], (instregex "VRNDSCALEPDZ256rm(b?)i(k?)(z?)")>; def: InstRW<[SKXWriteResGroup192], (instregex "VRNDSCALEPDZrm(b?)i(k?)(z?)")>; def: InstRW<[SKXWriteResGroup192], (instregex "VRNDSCALEPSZ256rm(b?)i(k?)(z?)")>; @@ -5619,6 +5628,15 @@ def: InstRW<[SKXWriteResGroup192], (instregex "VRNDSCALEPSZrm(b?)i(k?)(z?)")>; def: InstRW<[SKXWriteResGroup192], (instregex "VROUNDYPDm")>; def: InstRW<[SKXWriteResGroup192], (instregex "VROUNDYPSm")>; +def SKXWriteResGroup192_2 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 17; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup192_2], (instregex "VPMULLDYrm")>; +def: InstRW<[SKXWriteResGroup192_2], (instregex "VPMULLDZ256rm(b?)(k?)(z?)")>; +def: InstRW<[SKXWriteResGroup192_2], (instregex "VPMULLDZrm(b?)(k?)(z?)")>; + def SKXWriteResGroup193 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { let Latency = 15; let NumMicroOps = 4; |
