diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstructionSelector.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 2 |
3 files changed, 10 insertions, 7 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp index f8fc7cb0898..9952b5c4588 100644 --- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp +++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp @@ -239,7 +239,9 @@ bool MipsInstructionSelector::select(MachineInstr &I) { return true; } - if (I.getOpcode() == Mips::G_MUL) { + if (I.getOpcode() == Mips::G_MUL && + (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() == + Mips::GPRBRegBankID)) { MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) .add(I.getOperand(0)) .add(I.getOperand(1)) diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index ce203b39929..3c931d77e94 100644 --- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -61,11 +61,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { const LLT v2s64 = LLT::vector(2, 64); const LLT p0 = LLT::pointer(0, 32); - getActionDefinitionsBuilder(G_MUL) - .legalFor({s32}) - .clampScalar(0, s32, s32); - - getActionDefinitionsBuilder({G_ADD, G_SUB}) + getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL}) .legalIf([=, &ST](const LegalityQuery &Query) { if (CheckTyN(0, Query, {s32})) return true; @@ -377,6 +373,11 @@ bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI, return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_W, MIRBuilder, ST); case Intrinsic::mips_subvi_d: return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_D, MIRBuilder, ST); + case Intrinsic::mips_mulv_b: + case Intrinsic::mips_mulv_h: + case Intrinsic::mips_mulv_w: + case Intrinsic::mips_mulv_d: + return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_MUL, MIRBuilder, ST); default: break; } diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp index 51a1cf3fa48..f8531f88856 100644 --- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -437,7 +437,6 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { switch (Opc) { case G_TRUNC: - case G_MUL: case G_UMULH: case G_ZEXTLOAD: case G_SEXTLOAD: @@ -460,6 +459,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { break; case G_ADD: case G_SUB: + case G_MUL: OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; if (Op0Size == 128) OperandsMapping = getMSAMapping(MF); |
