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-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.cpp15
1 files changed, 2 insertions, 13 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index ab0f069dc71..276ceae7cdc 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -7852,7 +7852,8 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
MIB->getOperand(0).setReg(SrcReg);
return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
}
- case X86::AVX512_256_SET0: {
+ case X86::AVX512_256_SET0:
+ case X86::AVX512_512_SET0: {
bool HasVLX = Subtarget.hasVLX();
unsigned SrcReg = MIB->getOperand(0).getReg();
const TargetRegisterInfo *TRI = &getRegisterInfo();
@@ -7866,18 +7867,6 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
}
return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
}
- case X86::AVX512_512_SET0: {
- const TargetRegisterInfo *TRI = &getRegisterInfo();
- unsigned SrcReg = MIB->getOperand(0).getReg();
- if (TRI->getEncodingValue(SrcReg) < 16) {
- unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
- MIB->getOperand(0).setReg(XReg);
- Expand2AddrUndef(MIB, get(X86::VXORPSrr));
- MIB.addReg(SrcReg, RegState::ImplicitDefine);
- return true;
- }
- return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
- }
case X86::V_SETALLONES:
return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
case X86::AVX2_SETALLONES:
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