2 files changed, 31 insertions, 56 deletions

diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 4d4e2dae01e..666e0989d9d 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -628,7 +628,7 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   bool SPRDest = ARM::SPRRegClass.contains(DestReg);
   bool SPRSrc  = ARM::SPRRegClass.contains(SrcReg);
 
-  unsigned Opc;
+  unsigned Opc = 0;
   if (SPRDest && SPRSrc) {
     Opc = ARM::VMOVS;
 
@@ -668,17 +668,38 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     Opc = ARM::VORRq;
   else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
     Opc = ARM::VMOVQQ;
-  else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
-    Opc = ARM::VMOVQQQQ;
-  else
-    llvm_unreachable("Impossible reg-to-reg copy");
 
-  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
-  MIB.addReg(SrcReg, getKillRegState(KillSrc));
-  if (Opc == ARM::VORRq)
+  if (Opc) {
+    MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
     MIB.addReg(SrcReg, getKillRegState(KillSrc));
-  if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
-    AddDefaultPred(MIB);
+    if (Opc == ARM::VORRq)
+      MIB.addReg(SrcReg, getKillRegState(KillSrc));
+    if (Opc != ARM::VMOVQQ)
+      AddDefaultPred(MIB);
+    return;
+  }
+
+  // Expand the MOVQQQQ pseudo instruction in place.
+  if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
+    const TargetRegisterInfo *TRI = &getRegisterInfo();
+    assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
+    for (unsigned i = ARM::qsub_0, e = ARM::qsub_3 + 1; i != e; ++i) { 
+      unsigned Dst = TRI->getSubReg(DestReg, i);
+      unsigned Src = TRI->getSubReg(SrcReg, i);
+      MachineInstrBuilder Mov =
+        AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq))
+                       .addReg(Dst, RegState::Define)
+                       .addReg(Src, getKillRegState(KillSrc))
+                       .addReg(Src, getKillRegState(KillSrc)));
+      if (i == ARM::qsub_3) {
+        Mov->addRegisterDefined(DestReg, TRI);
+        if (KillSrc)
+          Mov->addRegisterKilled(SrcReg, TRI);
+      }
+    }
+    return;
+  }
+  llvm_unreachable("Impossible reg-to-reg copy");
 }
 
 static const
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 0f92d66adee..52c8ab7e181 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -998,52 +998,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
       return true;
     }
 
-    case ARM::VMOVQQQQ: {
-      unsigned DstReg = MI.getOperand(0).getReg();
-      bool DstIsDead = MI.getOperand(0).isDead();
-      unsigned Dst0 = TRI->getSubReg(DstReg, ARM::qsub_0);
-      unsigned Dst1 = TRI->getSubReg(DstReg, ARM::qsub_1);
-      unsigned Dst2 = TRI->getSubReg(DstReg, ARM::qsub_2);
-      unsigned Dst3 = TRI->getSubReg(DstReg, ARM::qsub_3);
-      unsigned SrcReg = MI.getOperand(1).getReg();
-      bool SrcIsKill = MI.getOperand(1).isKill();
-      unsigned Src0 = TRI->getSubReg(SrcReg, ARM::qsub_0);
-      unsigned Src1 = TRI->getSubReg(SrcReg, ARM::qsub_1);
-      unsigned Src2 = TRI->getSubReg(SrcReg, ARM::qsub_2);
-      unsigned Src3 = TRI->getSubReg(SrcReg, ARM::qsub_3);
-      MachineInstrBuilder Mov0 =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(Dst0,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(Src0, getKillRegState(SrcIsKill))
-                       .addReg(Src0, getKillRegState(SrcIsKill)));
-      MachineInstrBuilder Mov1 =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(Dst1,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(Src1, getKillRegState(SrcIsKill))
-                       .addReg(Src1, getKillRegState(SrcIsKill)));
-      MachineInstrBuilder Mov2 =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(Dst2,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(Src2, getKillRegState(SrcIsKill))
-                       .addReg(Src2, getKillRegState(SrcIsKill)));
-      MachineInstrBuilder Mov3 =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(Dst3,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(Src3, getKillRegState(SrcIsKill))
-                       .addReg(Src3, getKillRegState(SrcIsKill)));
-      TransferImpOps(MI, Mov0, Mov3);
-      MI.eraseFromParent();
-      return true;
-    }
-
     case ARM::VLDMQIA: {
       unsigned NewOpc = ARM::VLDMDIA;
       MachineInstrBuilder MIB =