diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/Mips32r6InstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 16 |
4 files changed, 9 insertions, 26 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 9c121e56a84..cb3a5918c7e 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1144,15 +1144,7 @@ public: (R0 == Mips::A0 && R1 == Mips::S6) || (R0 == Mips::A0 && R1 == Mips::A1) || (R0 == Mips::A0 && R1 == Mips::A2) || - (R0 == Mips::A0 && R1 == Mips::A3) || - (R0 == Mips::A1_64 && R1 == Mips::A2_64) || - (R0 == Mips::A1_64 && R1 == Mips::A3_64) || - (R0 == Mips::A2_64 && R1 == Mips::A3_64) || - (R0 == Mips::A0_64 && R1 == Mips::S5_64) || - (R0 == Mips::A0_64 && R1 == Mips::S6_64) || - (R0 == Mips::A0_64 && R1 == Mips::A1_64) || - (R0 == Mips::A0_64 && R1 == Mips::A2_64) || - (R0 == Mips::A0_64 && R1 == Mips::A3_64)) + (R0 == Mips::A0 && R1 == Mips::A3)) return true; return false; diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 1ae9b791980..4e92e1a9ad0 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -1025,9 +1025,6 @@ def : MipsInstAlias<"tltu $rs, $rt", (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : MipsInstAlias<"tne $rs, $rt", (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; -def : MipsInstAlias<"rotr $rt, $imm", - (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>; -def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>; def : MipsInstAlias<"slt $rs, $rt, $imm", (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; } diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td index f249ff2d610..ea75cc5bba2 100644 --- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td @@ -757,9 +757,7 @@ def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6; def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; -let AdditionalPredicates = [NotInMicroMips] in { - def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; -} +def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6; def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; @@ -793,9 +791,9 @@ def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6; let AdditionalPredicates = [NotInMicroMips] in { def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT; def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT; - def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; } +def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; let AdditionalPredicates = [NotInMicroMips] in { diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index a16ca0f0241..ee92118a2ab 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1707,13 +1707,11 @@ def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, SRLV_FM<7, 0>; // Rotate Instructions -let AdditionalPredicates = [NotInMicroMips] in { - def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, - immZExt5>, - SRA_FM<2, 1>, ISA_MIPS32R2; - def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, - SRLV_FM<6, 1>, ISA_MIPS32R2; -} +def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, + immZExt5>, + SRA_FM<2, 1>, ISA_MIPS32R2; +def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, + SRLV_FM<6, 1>, ISA_MIPS32R2; /// Load and Store Instructions /// aligned @@ -2230,9 +2228,7 @@ def : MipsInstAlias<"beqz $rs,$offset", (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; def : MipsInstAlias<"beqzl $rs,$offset", (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; -let AdditionalPredicates = [NotInMicroMips] in { - def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; -} +def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; def : MipsInstAlias<"break", (BREAK 0, 0), 1>; def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; |
