diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonPatterns.td | 48 |
3 files changed, 25 insertions, 41 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 0e0da2ddc40..13517aa565b 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2256,9 +2256,7 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH"; case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN"; case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU"; - case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP"; case HexagonISD::INSERT: return "HexagonISD::INSERT"; - case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP"; case HexagonISD::JT: return "HexagonISD::JT"; case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG"; case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN"; @@ -2707,11 +2705,8 @@ HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV, IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32); SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, DAG.getConstant(ElemWidth, dl, MVT::i32)); - // EXTRACTURP takes width/offset in a 64-bit pair. - SDValue CombV = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, - {WidthV, OffV}); - ExtV = DAG.getNode(HexagonISD::EXTRACTURP, dl, ScalarTy, - {VecV, CombV}); + ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy, + {VecV, WidthV, OffV}); } // Cast ExtV to the requested result type. @@ -2752,11 +2747,8 @@ HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV, if (ty(IdxV) != MVT::i32) IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32); SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV); - // INSERTRP takes width/offset in a 64-bit pair. - SDValue CombV = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, - {WidthV, OffV}); - InsV = DAG.getNode(HexagonISD::INSERTRP, dl, ScalarTy, - {VecV, ValV, CombV}); + InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy, + {VecV, ValV, WidthV, OffV}); } return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index 732834b464b..66214a409b3 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -57,9 +57,7 @@ namespace HexagonISD { VLSR, INSERT, - INSERTRP, EXTRACTU, - EXTRACTURP, VCOMBINE, VPACKE, VPACKO, diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td index 98229f4fa64..2224fd22034 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -892,40 +892,34 @@ let AddedComplexity = 100, Predicates = [HasV5T] in { def SDTHexagonINSERT: SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>; -def SDTHexagonINSERTRP: - SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, - SDTCisInt<0>, SDTCisVT<3, i64>]>; - def HexagonINSERT: SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>; -def HexagonINSERTRP: SDNode<"HexagonISD::INSERTRP", SDTHexagonINSERTRP>; -def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2), - (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>; -def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2), - (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>; -def: Pat<(HexagonINSERTRP I32:$Rs, I32:$Rt, I64:$Ru), - (S2_insert_rp I32:$Rs, I32:$Rt, I64:$Ru)>; -def: Pat<(HexagonINSERTRP I64:$Rs, I64:$Rt, I64:$Ru), - (S2_insertp_rp I64:$Rs, I64:$Rt, I64:$Ru)>; +let AddedComplexity = 10 in { + def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2), + (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>; + def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2), + (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>; +} +def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, I32:$Width, I32:$Off), + (S2_insert_rp I32:$Rs, I32:$Rt, (Combinew $Width, $Off))>; +def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, I32:$Width, I32:$Off), + (S2_insertp_rp I64:$Rs, I64:$Rt, (Combinew $Width, $Off))>; def SDTHexagonEXTRACTU : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>, SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; -def SDTHexagonEXTRACTURP - : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>, - SDTCisVT<2, i64>]>; - def HexagonEXTRACTU: SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>; -def HexagonEXTRACTURP: SDNode<"HexagonISD::EXTRACTURP", SDTHexagonEXTRACTURP>; - -def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5), - (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>; -def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6), - (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>; -def: Pat<(HexagonEXTRACTURP I32:$Rs, I64:$Rt), - (S2_extractu_rp I32:$Rs, I64:$Rt)>; -def: Pat<(HexagonEXTRACTURP I64:$Rs, I64:$Rt), - (S2_extractup_rp I64:$Rs, I64:$Rt)>; + +let AddedComplexity = 10 in { + def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5), + (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>; + def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6), + (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>; +} +def: Pat<(HexagonEXTRACTU I32:$Rs, I32:$Width, I32:$Off), + (S2_extractu_rp I32:$Rs, (Combinew $Width, $Off))>; +def: Pat<(HexagonEXTRACTU I64:$Rs, I32:$Width, I32:$Off), + (S2_extractup_rp I64:$Rs, (Combinew $Width, $Off))>; def SDTHexagonVSPLAT: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; |
