diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index 51333181559..973a0787da7 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -207,6 +207,11 @@ multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> { defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond, !add(baseInst, 1)>; } +multiclass SIMDAbs<ValueType vec_t, string vec, bits<32> simdop> { + defm ABS_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins), + [(set (vec_t V128:$dst), (vec_t (fabs V128:$vec)))], + vec#".abs\t$dst, $vec", vec#".abs", simdop>; +} let Defs = [ARGUMENTS] in { defm "" : ConstVec<v16i8, @@ -363,6 +368,9 @@ defm GE_S : SIMDConditionInt<"ge_s", SETGE, 106, 2>; defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 107, 2>; defm GE : SIMDConditionFP<"ge", SETOGE, 112>; +defm "" : SIMDAbs<v4f32, "f32x4", 116>; +defm "" : SIMDAbs<v2f64, "f64x2", 117>; + } // Defs = [ARGUMENTS] // Def load and store patterns from WebAssemblyInstrMemory.td for vector types |
