diff options
Diffstat (limited to 'llvm/lib/Target')
28 files changed, 150 insertions, 150 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp b/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp index e8f113ec083..7b4ab7cc1a3 100644 --- a/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp +++ b/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp @@ -740,7 +740,7 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) { if (TagMap.count(NewTag)) continue; - DEBUG(dbgs() << "Changing base reg to: " << PrintReg(ScratchReg, TRI) + DEBUG(dbgs() << "Changing base reg to: " << printReg(ScratchReg, TRI) << '\n'); // Rewrite: @@ -760,7 +760,7 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) { // well to update the real base register. if (LdI.IsPrePost) { DEBUG(dbgs() << "Doing post MOV of incremented reg: " - << PrintReg(ScratchReg, TRI) << '\n'); + << printReg(ScratchReg, TRI) << '\n'); MI.getOperand(0).setReg( ScratchReg); // Change tied operand pre/post update dest. BuildMI(*MBB, std::next(MachineBasicBlock::iterator(MI)), DL, diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index ab7e35d6fa0..257e6f6e946 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1208,7 +1208,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:"; for (unsigned Reg : SavedRegs.set_bits()) - dbgs() << ' ' << PrintReg(Reg, RegInfo); + dbgs() << ' ' << printReg(Reg, RegInfo); dbgs() << "\n";); // If any callee-saved registers are used, the frame cannot be eliminated. @@ -1233,7 +1233,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, // here. if (BigStack) { if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) { - DEBUG(dbgs() << "Spilling " << PrintReg(UnspilledCSGPR, RegInfo) + DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo) << " to get a scratch register.\n"); SavedRegs.set(UnspilledCSGPR); // MachO's compact unwind format relies on all registers being stored in diff --git a/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp b/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp index fe4ef4b40ec..cfd89ad1cab 100644 --- a/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp +++ b/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp @@ -247,13 +247,13 @@ void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, // Do some Chain management if (Chains.count(Ra)) { if (Rd != Ra) { - DEBUG(dbgs() << "Moving acc chain from " << PrintReg(Ra, TRI) << " to " - << PrintReg(Rd, TRI) << '\n';); + DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI) << " to " + << printReg(Rd, TRI) << '\n';); Chains.remove(Ra); Chains.insert(Rd); } } else { - DEBUG(dbgs() << "Creating new acc chain for " << PrintReg(Rd, TRI) + DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI) << '\n';); Chains.insert(Rd); } @@ -340,7 +340,7 @@ void A57ChainingConstraint::apply(PBQPRAGraph &G) { for (auto r : Chains) { SmallVector<unsigned, 8> toDel; if(regJustKilledBefore(LIs, r, MI)) { - DEBUG(dbgs() << "Killing chain " << PrintReg(r, TRI) << " at "; + DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at "; MI.print(dbgs());); toDel.push_back(r); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp index 3533ec30505..dcca3a2fab9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp @@ -27,7 +27,7 @@ void ArgDescriptor::print(raw_ostream &OS, } if (isRegister()) - OS << "Reg " << PrintReg(getRegister(), TRI) << '\n'; + OS << "Reg " << printReg(getRegister(), TRI) << '\n'; else OS << "Stack offset " << getStackOffset() << '\n'; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp index 3aff9ce2196..879f65e1228 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp @@ -267,10 +267,10 @@ LLVM_DUMP_METHOD void PHILinearize::dump(MachineRegisterInfo *MRI) { dbgs() << "=PHIInfo Start=\n"; for (auto PII : this->PHIInfo) { PHIInfoElementT &Element = *PII; - dbgs() << "Dest: " << PrintReg(Element.DestReg, TRI) + dbgs() << "Dest: " << printReg(Element.DestReg, TRI) << " Sources: {"; for (auto &SI : Element.Sources) { - dbgs() << PrintReg(SI.first, TRI) << "(BB#" + dbgs() << printReg(SI.first, TRI) << "(BB#" << SI.second->getNumber() << "),"; } dbgs() << "}\n"; @@ -500,8 +500,8 @@ public: void dump(const TargetRegisterInfo *TRI, int depth = 0) override { dumpDepth(depth); dbgs() << "MBB: " << getMBB()->getNumber(); - dbgs() << " In: " << PrintReg(getBBSelectRegIn(), TRI); - dbgs() << ", Out: " << PrintReg(getBBSelectRegOut(), TRI) << "\n"; + dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI); + dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n"; } }; @@ -550,8 +550,8 @@ public: void dump(const TargetRegisterInfo *TRI, int depth = 0) override { dumpDepth(depth); dbgs() << "Region: " << (void *)Region; - dbgs() << " In: " << PrintReg(getBBSelectRegIn(), TRI); - dbgs() << ", Out: " << PrintReg(getBBSelectRegOut(), TRI) << "\n"; + dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI); + dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n"; dumpDepth(depth); if (getSucc()) @@ -695,18 +695,18 @@ void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg, const TargetRegisterInfo *TRI, PHILinearize &PHIInfo) { if (TRI->isVirtualRegister(Reg)) { - DEBUG(dbgs() << "Considering Register: " << PrintReg(Reg, TRI) << "\n"); + DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) << "\n"); // If this is a source register to a PHI we are chaining, it // must be live out. if (PHIInfo.isSource(Reg)) { - DEBUG(dbgs() << "Add LiveOut (PHI): " << PrintReg(Reg, TRI) << "\n"); + DEBUG(dbgs() << "Add LiveOut (PHI): " << printReg(Reg, TRI) << "\n"); addLiveOut(Reg); } else { // If this is live out of the MBB for (auto &UI : MRI->use_operands(Reg)) { if (UI.getParent()->getParent() != MBB) { DEBUG(dbgs() << "Add LiveOut (MBB BB#" << MBB->getNumber() - << "): " << PrintReg(Reg, TRI) << "\n"); + << "): " << printReg(Reg, TRI) << "\n"); addLiveOut(Reg); } else { // If the use is in the same MBB we have to make sure @@ -717,7 +717,7 @@ void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg, MIE = UseInstr->getParent()->instr_end(); MII != MIE; ++MII) { if ((&(*MII)) == DefInstr) { - DEBUG(dbgs() << "Add LiveOut (Loop): " << PrintReg(Reg, TRI) + DEBUG(dbgs() << "Add LiveOut (Loop): " << printReg(Reg, TRI) << "\n"); addLiveOut(Reg); } @@ -734,11 +734,11 @@ void LinearizedRegion::storeLiveOutRegRegion(RegionMRT *Region, unsigned Reg, const TargetRegisterInfo *TRI, PHILinearize &PHIInfo) { if (TRI->isVirtualRegister(Reg)) { - DEBUG(dbgs() << "Considering Register: " << PrintReg(Reg, TRI) << "\n"); + DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) << "\n"); for (auto &UI : MRI->use_operands(Reg)) { if (!Region->contains(UI.getParent()->getParent())) { DEBUG(dbgs() << "Add LiveOut (Region " << (void *)Region - << "): " << PrintReg(Reg, TRI) << "\n"); + << "): " << printReg(Reg, TRI) << "\n"); addLiveOut(Reg); } } @@ -775,7 +775,7 @@ void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB, unsigned PHIReg = getPHISourceReg(PHI, i); DEBUG(dbgs() << "Add LiveOut (PhiSource BB#" << MBB->getNumber() << " -> BB#" << (*SI)->getNumber() - << "): " << PrintReg(PHIReg, TRI) << "\n"); + << "): " << printReg(PHIReg, TRI) << "\n"); addLiveOut(PHIReg); } } @@ -844,7 +844,7 @@ void LinearizedRegion::storeLiveOuts(RegionMRT *Region, if (Region->contains(getPHIPred(PHI, i))) { unsigned PHIReg = getPHISourceReg(PHI, i); DEBUG(dbgs() << "Add Region LiveOut (" << (void *)Region - << "): " << PrintReg(PHIReg, TRI) << "\n"); + << "): " << printReg(PHIReg, TRI) << "\n"); addLiveOut(PHIReg); } } @@ -867,10 +867,10 @@ void LinearizedRegion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) { } OS << "} (" << Entry->getNumber() << ", " << (Exit == nullptr ? -1 : Exit->getNumber()) - << "): In:" << PrintReg(getBBSelectRegIn(), TRI) - << " Out:" << PrintReg(getBBSelectRegOut(), TRI) << " {"; + << "): In:" << printReg(getBBSelectRegIn(), TRI) + << " Out:" << printReg(getBBSelectRegOut(), TRI) << " {"; for (auto &LI : LiveOuts) { - OS << PrintReg(LI, TRI) << " "; + OS << printReg(LI, TRI) << " "; } OS << "} \n"; } @@ -909,8 +909,8 @@ void LinearizedRegion::replaceRegister(unsigned Register, unsigned NewRegister, assert(Register != NewRegister && "Cannot replace a reg with itself"); DEBUG(dbgs() << "Pepareing to replace register (region): " - << PrintReg(Register, MRI->getTargetRegisterInfo()) << " with " - << PrintReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); + << printReg(Register, MRI->getTargetRegisterInfo()) << " with " + << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); // If we are replacing outside, we also need to update the LiveOuts if (ReplaceOutside && @@ -946,14 +946,14 @@ void LinearizedRegion::replaceRegister(unsigned Register, unsigned NewRegister, if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) { DEBUG(dbgs() << "Trying to substitute physical register: " - << PrintReg(NewRegister, MRI->getTargetRegisterInfo()) + << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); llvm_unreachable("Cannot substitute physical registers"); } else { DEBUG(dbgs() << "Replacing register (region): " - << PrintReg(Register, MRI->getTargetRegisterInfo()) + << printReg(Register, MRI->getTargetRegisterInfo()) << " with " - << PrintReg(NewRegister, MRI->getTargetRegisterInfo()) + << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); O.setReg(NewRegister); } @@ -1022,16 +1022,16 @@ void LinearizedRegion::removeFalseRegisterKills(MachineRegisterInfo *MRI) { continue; if (!MRI->hasOneDef(Reg)) { DEBUG(this->getEntry()->getParent()->dump()); - DEBUG(dbgs() << PrintReg(Reg, TRI) << "\n"); + DEBUG(dbgs() << printReg(Reg, TRI) << "\n"); } if (MRI->def_begin(Reg) == MRI->def_end()) { DEBUG(dbgs() << "Register " - << PrintReg(Reg, MRI->getTargetRegisterInfo()) + << printReg(Reg, MRI->getTargetRegisterInfo()) << " has NO defs\n"); } else if (!MRI->hasOneDef(Reg)) { DEBUG(dbgs() << "Register " - << PrintReg(Reg, MRI->getTargetRegisterInfo()) + << printReg(Reg, MRI->getTargetRegisterInfo()) << " has multiple defs\n"); } @@ -1041,7 +1041,7 @@ void LinearizedRegion::removeFalseRegisterKills(MachineRegisterInfo *MRI) { bool UseIsOutsideDefMBB = Def->getParent()->getParent() != MBB; if (UseIsOutsideDefMBB && UseOperand->isKill()) { DEBUG(dbgs() << "Removing kill flag on register: " - << PrintReg(Reg, TRI) << "\n"); + << printReg(Reg, TRI) << "\n"); UseOperand->setIsKill(false); } } @@ -1449,7 +1449,7 @@ bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI, unsigned *ReplaceReg) { DEBUG(dbgs() << "Shrink PHI: "); DEBUG(PHI.dump()); - DEBUG(dbgs() << " to " << PrintReg(getPHIDestReg(PHI), TRI) + DEBUG(dbgs() << " to " << printReg(getPHIDestReg(PHI), TRI) << "<def> = PHI("); bool Replaced = false; @@ -1480,7 +1480,7 @@ bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI, if (SourceMBB) { MIB.addReg(CombinedSourceReg); MIB.addMBB(SourceMBB); - DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#" << SourceMBB->getNumber()); } @@ -1492,7 +1492,7 @@ bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI, MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MIB.addReg(SourceReg); MIB.addMBB(SourcePred); - DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#" << SourcePred->getNumber()); } DEBUG(dbgs() << ")\n"); @@ -1506,7 +1506,7 @@ void AMDGPUMachineCFGStructurizer::replacePHI( SmallVector<unsigned, 2> &PHIRegionIndices) { DEBUG(dbgs() << "Replace PHI: "); DEBUG(PHI.dump()); - DEBUG(dbgs() << " with " << PrintReg(getPHIDestReg(PHI), TRI) + DEBUG(dbgs() << " with " << printReg(getPHIDestReg(PHI), TRI) << "<def> = PHI("); bool HasExternalEdge = false; @@ -1524,7 +1524,7 @@ void AMDGPUMachineCFGStructurizer::replacePHI( getPHIDestReg(PHI)); MIB.addReg(CombinedSourceReg); MIB.addMBB(LastMerge); - DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#" << LastMerge->getNumber()); for (unsigned i = 0; i < NumInputs; ++i) { if (isPHIRegionIndex(PHIRegionIndices, i)) { @@ -1534,7 +1534,7 @@ void AMDGPUMachineCFGStructurizer::replacePHI( MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MIB.addReg(SourceReg); MIB.addMBB(SourcePred); - DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#" << SourcePred->getNumber()); } DEBUG(dbgs() << ")\n"); @@ -1562,17 +1562,17 @@ void AMDGPUMachineCFGStructurizer::replaceEntryPHI( if (NumNonRegionInputs == 0) { auto DestReg = getPHIDestReg(PHI); replaceRegisterWith(DestReg, CombinedSourceReg); - DEBUG(dbgs() << " register " << PrintReg(CombinedSourceReg, TRI) << "\n"); + DEBUG(dbgs() << " register " << printReg(CombinedSourceReg, TRI) << "\n"); PHI.eraseFromParent(); } else { - DEBUG(dbgs() << PrintReg(getPHIDestReg(PHI), TRI) << "<def> = PHI("); + DEBUG(dbgs() << printReg(getPHIDestReg(PHI), TRI) << "<def> = PHI("); MachineBasicBlock *MBB = PHI.getParent(); MachineInstrBuilder MIB = BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI), getPHIDestReg(PHI)); MIB.addReg(CombinedSourceReg); MIB.addMBB(IfMBB); - DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#" << IfMBB->getNumber()); unsigned NumInputs = getPHINumInputs(PHI); for (unsigned i = 0; i < NumInputs; ++i) { @@ -1583,7 +1583,7 @@ void AMDGPUMachineCFGStructurizer::replaceEntryPHI( MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MIB.addReg(SourceReg); MIB.addMBB(SourcePred); - DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#" << SourcePred->getNumber()); } DEBUG(dbgs() << ")\n"); @@ -1608,7 +1608,7 @@ void AMDGPUMachineCFGStructurizer::replaceLiveOutRegs( } } - DEBUG(dbgs() << "Register " << PrintReg(Reg, TRI) << " is " + DEBUG(dbgs() << "Register " << printReg(Reg, TRI) << " is " << (IsDead ? "dead" : "alive") << " after PHI replace\n"); if (IsDead) { LRegion->removeLiveOut(Reg); @@ -1750,9 +1750,9 @@ void AMDGPUMachineCFGStructurizer::insertMergePHI(MachineBasicBlock *IfBB, return; } DEBUG(dbgs() << "Merge PHI (BB#" << MergeBB->getNumber() - << "): " << PrintReg(DestRegister, TRI) << "<def> = PHI(" - << PrintReg(IfSourceRegister, TRI) << ", BB#" - << IfBB->getNumber() << PrintReg(CodeSourceRegister, TRI) + << "): " << printReg(DestRegister, TRI) << "<def> = PHI(" + << printReg(IfSourceRegister, TRI) << ", BB#" + << IfBB->getNumber() << printReg(CodeSourceRegister, TRI) << ", BB#" << CodeBB->getNumber() << ")\n"); const DebugLoc &DL = MergeBB->findDebugLoc(MergeBB->begin()); MachineInstrBuilder MIB = BuildMI(*MergeBB, MergeBB->instr_begin(), DL, @@ -1936,10 +1936,10 @@ void AMDGPUMachineCFGStructurizer::rewriteCodeBBTerminator(MachineBasicBlock *Co MachineInstr *AMDGPUMachineCFGStructurizer::getDefInstr(unsigned Reg) { if (MRI->def_begin(Reg) == MRI->def_end()) { - DEBUG(dbgs() << "Register " << PrintReg(Reg, MRI->getTargetRegisterInfo()) + DEBUG(dbgs() << "Register " << printReg(Reg, MRI->getTargetRegisterInfo()) << " has NO defs\n"); } else if (!MRI->hasOneDef(Reg)) { - DEBUG(dbgs() << "Register " << PrintReg(Reg, MRI->getTargetRegisterInfo()) + DEBUG(dbgs() << "Register " << printReg(Reg, MRI->getTargetRegisterInfo()) << " has multiple defs\n"); DEBUG(dbgs() << "DEFS BEGIN:\n"); for (auto DI = MRI->def_begin(Reg), DE = MRI->def_end(); DI != DE; ++DI) { @@ -2023,7 +2023,7 @@ void AMDGPUMachineCFGStructurizer::rewriteLiveOutRegs(MachineBasicBlock *IfBB, } for (auto LI : OldLiveOuts) { - DEBUG(dbgs() << "LiveOut: " << PrintReg(LI, TRI)); + DEBUG(dbgs() << "LiveOut: " << printReg(LI, TRI)); if (!containsDef(CodeBB, InnerRegion, LI) || (!IsSingleBB && (getDefInstr(LI)->getParent() == LRegion->getExit()))) { // If the register simly lives through the CodeBB, we don't have @@ -2049,7 +2049,7 @@ void AMDGPUMachineCFGStructurizer::rewriteLiveOutRegs(MachineBasicBlock *IfBB, unsigned IfSourceReg = MRI->createVirtualRegister(RegClass); // Create initializer, this value is never used, but is needed // to satisfy SSA. - DEBUG(dbgs() << "Initializer for reg: " << PrintReg(Reg) << "\n"); + DEBUG(dbgs() << "Initializer for reg: " << printReg(Reg) << "\n"); TII->materializeImmediate(*IfBB, IfBB->getFirstTerminator(), DebugLoc(), IfSourceReg, 0); @@ -2146,7 +2146,7 @@ void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegio const DebugLoc &DL = Entry->findDebugLoc(Entry->begin()); MachineInstrBuilder MIB = BuildMI(*Entry, Entry->instr_begin(), DL, TII->get(TargetOpcode::PHI), DestReg); - DEBUG(dbgs() << "Entry PHI " << PrintReg(DestReg, TRI) << "<def> = PHI("); + DEBUG(dbgs() << "Entry PHI " << printReg(DestReg, TRI) << "<def> = PHI("); unsigned CurrentBackedgeReg = 0; @@ -2171,16 +2171,16 @@ void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegio BackedgePHI.addMBB((*SRI).second); CurrentBackedgeReg = NewBackedgeReg; DEBUG(dbgs() << "Inserting backedge PHI: " - << PrintReg(NewBackedgeReg, TRI) << "<def> = PHI(" - << PrintReg(CurrentBackedgeReg, TRI) << ", BB#" + << printReg(NewBackedgeReg, TRI) << "<def> = PHI(" + << printReg(CurrentBackedgeReg, TRI) << ", BB#" << getPHIPred(*PHIDefInstr, 0)->getNumber() << ", " - << PrintReg(getPHISourceReg(*PHIDefInstr, 1), TRI) + << printReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << ", BB#" << (*SRI).second->getNumber()); } } else { MIB.addReg(SourceReg); MIB.addMBB((*SRI).second); - DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#" << (*SRI).second->getNumber() << ", "); } } @@ -2189,7 +2189,7 @@ void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegio if (CurrentBackedgeReg != 0) { MIB.addReg(CurrentBackedgeReg); MIB.addMBB(Exit); - DEBUG(dbgs() << PrintReg(CurrentBackedgeReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", BB#" << Exit->getNumber() << ")\n"); } else { DEBUG(dbgs() << ")\n"); @@ -2220,7 +2220,7 @@ void AMDGPUMachineCFGStructurizer::replaceRegisterWith(unsigned Register, ++I; if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) { DEBUG(dbgs() << "Trying to substitute physical register: " - << PrintReg(NewRegister, MRI->getTargetRegisterInfo()) + << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); llvm_unreachable("Cannot substitute physical registers"); // We don't handle physical registers, but if we need to @@ -2228,9 +2228,9 @@ void AMDGPUMachineCFGStructurizer::replaceRegisterWith(unsigned Register, // O.substPhysReg(NewRegister, *TRI); } else { DEBUG(dbgs() << "Replacing register: " - << PrintReg(Register, MRI->getTargetRegisterInfo()) + << printReg(Register, MRI->getTargetRegisterInfo()) << " with " - << PrintReg(NewRegister, MRI->getTargetRegisterInfo()) + << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); O.setReg(NewRegister); } @@ -2248,11 +2248,11 @@ void AMDGPUMachineCFGStructurizer::resolvePHIInfos(MachineBasicBlock *FunctionEn for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE; ++DRI) { unsigned DestReg = *DRI; - DEBUG(dbgs() << "DestReg: " << PrintReg(DestReg, TRI) << "\n"); + DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) << "\n"); auto SRI = PHIInfo.sources_begin(DestReg); unsigned SourceReg = (*SRI).first; - DEBUG(dbgs() << "DestReg: " << PrintReg(DestReg, TRI) - << " SourceReg: " << PrintReg(SourceReg, TRI) << "\n"); + DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) + << " SourceReg: " << printReg(SourceReg, TRI) << "\n"); assert(PHIInfo.sources_end(DestReg) == ++SRI && "More than one phi source in entry node"); @@ -2439,14 +2439,14 @@ void AMDGPUMachineCFGStructurizer::splitLoopPHI(MachineInstr &PHI, MachineInstrBuilder MIB = BuildMI(*EntrySucc, EntrySucc->instr_begin(), PHI.getDebugLoc(), TII->get(TargetOpcode::PHI), NewDestReg); - DEBUG(dbgs() << "Split Entry PHI " << PrintReg(NewDestReg, TRI) + DEBUG(dbgs() << "Split Entry PHI " << printReg(NewDestReg, TRI) << "<def> = PHI("); MIB.addReg(PHISource); MIB.addMBB(Entry); - DEBUG(dbgs() << PrintReg(PHISource, TRI) << ", BB#" << Entry->getNumber()); + DEBUG(dbgs() << printReg(PHISource, TRI) << ", BB#" << Entry->getNumber()); MIB.addReg(RegionSourceReg); MIB.addMBB(RegionSourceMBB); - DEBUG(dbgs() << " ," << PrintReg(RegionSourceReg, TRI) << ", BB#" + DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", BB#" << RegionSourceMBB->getNumber() << ")\n"); } @@ -2669,9 +2669,9 @@ bool AMDGPUMachineCFGStructurizer::structurizeComplexRegion(RegionMRT *Region) { BBSelectRegOut = Child->getBBSelectRegOut(); BBSelectRegIn = Child->getBBSelectRegIn(); - DEBUG(dbgs() << "BBSelectRegIn: " << PrintReg(BBSelectRegIn, TRI) + DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI) << "\n"); - DEBUG(dbgs() << "BBSelectRegOut: " << PrintReg(BBSelectRegOut, TRI) + DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI) << "\n"); MachineBasicBlock *IfEnd = CurrentMerge; @@ -2693,9 +2693,9 @@ bool AMDGPUMachineCFGStructurizer::structurizeComplexRegion(RegionMRT *Region) { BBSelectRegOut = Child->getBBSelectRegOut(); BBSelectRegIn = Child->getBBSelectRegIn(); - DEBUG(dbgs() << "BBSelectRegIn: " << PrintReg(BBSelectRegIn, TRI) + DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI) << "\n"); - DEBUG(dbgs() << "BBSelectRegOut: " << PrintReg(BBSelectRegOut, TRI) + DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI) << "\n"); MachineBasicBlock *IfEnd = CurrentMerge; @@ -2800,7 +2800,7 @@ void AMDGPUMachineCFGStructurizer::createLinearizedRegion(RegionMRT *Region, LinearizedRegion *LRegion = new LinearizedRegion(); if (SelectOut) { LRegion->addLiveOut(SelectOut); - DEBUG(dbgs() << "Add LiveOut (BBSelect): " << PrintReg(SelectOut, TRI) + DEBUG(dbgs() << "Add LiveOut (BBSelect): " << printReg(SelectOut, TRI) << "\n"); } LRegion->setRegionMRT(Region); diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp index 17ff2721130..1204f86e462 100644 --- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp +++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp @@ -49,7 +49,7 @@ void llvm::printLivesAt(SlotIndex SI, for (const auto &S : LI.subranges()) { if (!S.liveAt(SI)) continue; if (firstTime) { - dbgs() << " " << PrintReg(Reg, MRI.getTargetRegisterInfo()) + dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo()) << '\n'; firstTime = false; } @@ -441,12 +441,12 @@ static void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR, for (auto const &P : TrackedLR) { auto I = LISLR.find(P.first); if (I == LISLR.end()) { - dbgs() << " " << PrintReg(P.first, TRI) + dbgs() << " " << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second) << " isn't found in LIS reported set\n"; } else if (I->second != P.second) { - dbgs() << " " << PrintReg(P.first, TRI) + dbgs() << " " << printReg(P.first, TRI) << " masks doesn't match: LIS reported " << PrintLaneMask(I->second) << ", tracked " @@ -457,7 +457,7 @@ static void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR, for (auto const &P : LISLR) { auto I = TrackedLR.find(P.first); if (I == TrackedLR.end()) { - dbgs() << " " << PrintReg(P.first, TRI) + dbgs() << " " << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second) << " isn't found in tracked set\n"; } @@ -495,7 +495,7 @@ void GCNRPTracker::printLiveRegs(raw_ostream &OS, const LiveRegSet& LiveRegs, unsigned Reg = TargetRegisterInfo::index2VirtReg(I); auto It = LiveRegs.find(Reg); if (It != LiveRegs.end() && It->second.any()) - OS << ' ' << PrintVRegOrUnit(Reg, TRI) << ':' + OS << ' ' << printVRegOrUnit(Reg, TRI) << ':' << PrintLaneMask(It->second); } OS << '\n'; diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp index 5ffff2aa920..c13148bf0a2 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -595,11 +595,11 @@ void SIScheduleBlock::printDebug(bool full) { << LiveOutPressure[DAG->getVGPRSetID()] << "\n\n"; dbgs() << "LiveIns:\n"; for (unsigned Reg : LiveInRegs) - dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' '; + dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; dbgs() << "\nLiveOuts:\n"; for (unsigned Reg : LiveOutRegs) - dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' '; + dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; } dbgs() << "\nInstructions:\n"; @@ -1635,7 +1635,7 @@ SIScheduleBlock *SIScheduleBlockScheduler::pickBlock() { dbgs() << Block->getID() << ' '; dbgs() << "\nCurrent Live:\n"; for (unsigned Reg : LiveRegs) - dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' '; + dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; dbgs() << '\n'; dbgs() << "Current VGPRs: " << VregCurrentUsage << '\n'; dbgs() << "Current SGPRs: " << SregCurrentUsage << '\n'; diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp index 4f3fb978079..aa95161c1b6 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp @@ -281,7 +281,7 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { if (J->modifiesRegister(CopyToExec, TRI)) { if (SaveExecInst) { DEBUG(dbgs() << "Multiple instructions modify " - << PrintReg(CopyToExec, TRI) << '\n'); + << printReg(CopyToExec, TRI) << '\n'); SaveExecInst = nullptr; break; } diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp index 48d5a00d594..a299e32c03a 100644 --- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp +++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp @@ -294,7 +294,7 @@ void ARCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, "Only support 4-byte stores to stack now."); assert(ARC::GPR32RegClass.hasSubClassEq(RC) && "Only support GPR32 stores to stack now."); - DEBUG(dbgs() << "Created store reg=" << PrintReg(SrcReg, TRI) + DEBUG(dbgs() << "Created store reg=" << printReg(SrcReg, TRI) << " to FrameIndex=" << FrameIndex << "\n"); BuildMI(MBB, I, dl, get(ARC::ST_rs9)) .addReg(SrcReg, getKillRegState(isKill)) @@ -321,7 +321,7 @@ void ARCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, "Only support 4-byte loads from stack now."); assert(ARC::GPR32RegClass.hasSubClassEq(RC) && "Only support GPR32 stores to stack now."); - DEBUG(dbgs() << "Created load reg=" << PrintReg(DestReg, TRI) + DEBUG(dbgs() << "Created load reg=" << printReg(DestReg, TRI) << " from FrameIndex=" << FrameIndex << "\n"); BuildMI(MBB, I, dl, get(ARC::LD_rs9)) .addReg(DestReg, RegState::Define) diff --git a/llvm/lib/Target/ARC/ARCRegisterInfo.cpp b/llvm/lib/Target/ARC/ARCRegisterInfo.cpp index bed47a0eab5..59b22c559f2 100644 --- a/llvm/lib/Target/ARC/ARCRegisterInfo.cpp +++ b/llvm/lib/Target/ARC/ARCRegisterInfo.cpp @@ -66,8 +66,8 @@ static void ReplaceFrameIndex(MachineBasicBlock::iterator II, MBB.getParent()->getSubtarget().getRegisterInfo(); BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); assert(BaseReg && "Register scavenging failed."); - DEBUG(dbgs() << "Scavenged register " << PrintReg(BaseReg, TRI) - << " for FrameReg=" << PrintReg(FrameReg, TRI) + DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) + << " for FrameReg=" << printReg(FrameReg, TRI) << "+Offset=" << Offset << "\n"); (void)TRI; RS->setRegUsed(BaseReg); diff --git a/llvm/lib/Target/ARM/A15SDOptimizer.cpp b/llvm/lib/Target/ARM/A15SDOptimizer.cpp index ad3c6a6b760..34e41ba5410 100644 --- a/llvm/lib/Target/ARM/A15SDOptimizer.cpp +++ b/llvm/lib/Target/ARM/A15SDOptimizer.cpp @@ -273,7 +273,7 @@ unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) { MRI->getRegClass(MI->getOperand(1).getReg()); if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { DEBUG(dbgs() << "Subreg copy is compatible - returning "); - DEBUG(dbgs() << PrintReg(FullReg) << "\n"); + DEBUG(dbgs() << printReg(FullReg) << "\n"); eraseInstrWithNoUses(MI); return FullReg; } @@ -644,7 +644,7 @@ bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) { DEBUG(dbgs() << "Replacing operand " << **I << " with " - << PrintReg(NewReg) << "\n"); + << printReg(NewReg) << "\n"); (*I)->substVirtReg(NewReg, 0, *TRI); } } diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index 9d7b936a950..d60734ab144 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -1797,7 +1797,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) { if (!MF.getRegInfo().isLiveIn(Reg)) { --EntryRegDeficit; - DEBUG(dbgs() << PrintReg(Reg, TRI) + DEBUG(dbgs() << printReg(Reg, TRI) << " is unused argument register, EntryRegDeficit = " << EntryRegDeficit << "\n"); } @@ -1817,13 +1817,13 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { if (SavedRegs.test(Reg)) { --RegDeficit; - DEBUG(dbgs() << PrintReg(Reg, TRI) + DEBUG(dbgs() << printReg(Reg, TRI) << " is saved low register, RegDeficit = " << RegDeficit << "\n"); } else { AvailableRegs.push_back(Reg); DEBUG(dbgs() - << PrintReg(Reg, TRI) + << printReg(Reg, TRI) << " is non-saved low register, adding to AvailableRegs\n"); } } @@ -1845,7 +1845,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) { if (SavedRegs.test(Reg)) { ++RegDeficit; - DEBUG(dbgs() << PrintReg(Reg, TRI) + DEBUG(dbgs() << printReg(Reg, TRI) << " is saved high register, RegDeficit = " << RegDeficit << "\n"); } @@ -1875,7 +1875,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n"); for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) { unsigned Reg = AvailableRegs.pop_back_val(); - DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI) + DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) << " to make up reg deficit\n"); SavedRegs.set(Reg); NumGPRSpills++; @@ -1920,7 +1920,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, (STI.isTargetWindows() && Reg == ARM::R11) || isARMLowRegister(Reg) || Reg == ARM::LR) { SavedRegs.set(Reg); - DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI) + DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) << " to make up alignment\n"); if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg)) ExtraCSSpill = true; @@ -1930,7 +1930,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) { unsigned Reg = UnspilledCS2GPRs.front(); SavedRegs.set(Reg); - DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI) + DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) << " to make up alignment\n"); if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg)) ExtraCSSpill = true; diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp index 39b567b9a25..5e20d8ca0fd 100644 --- a/llvm/lib/Target/Hexagon/BitTracker.cpp +++ b/llvm/lib/Target/Hexagon/BitTracker.cpp @@ -182,7 +182,7 @@ namespace llvm { void BitTracker::print_cells(raw_ostream &OS) const { for (const std::pair<unsigned, RegisterCell> P : Map) - dbgs() << PrintReg(P.first, &ME.TRI) << " -> " << P.second << "\n"; + dbgs() << printReg(P.first, &ME.TRI) << " -> " << P.second << "\n"; } BitTracker::BitTracker(const MachineEvaluator &E, MachineFunction &F) @@ -794,14 +794,14 @@ void BT::visitPHI(const MachineInstr &PI) { RegisterRef RU = PI.getOperand(i); RegisterCell ResC = ME.getCell(RU, Map); if (Trace) - dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) + dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) << " cell: " << ResC << "\n"; Changed |= DefC.meet(ResC, DefRR.Reg); } if (Changed) { if (Trace) - dbgs() << "Output: " << PrintReg(DefRR.Reg, &ME.TRI, DefRR.Sub) + dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub) << " cell: " << DefC << "\n"; ME.putCell(DefRR, DefC, Map); visitUsesOf(DefRR.Reg); @@ -826,13 +826,13 @@ void BT::visitNonBranch(const MachineInstr &MI) { if (!MO.isReg() || !MO.isUse()) continue; RegisterRef RU(MO); - dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) + dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) << " cell: " << ME.getCell(RU, Map) << "\n"; } dbgs() << "Outputs:\n"; for (const std::pair<unsigned, RegisterCell> &P : ResMap) { RegisterRef RD(P.first); - dbgs() << " " << PrintReg(P.first, &ME.TRI) << " cell: " + dbgs() << " " << printReg(P.first, &ME.TRI) << " cell: " << ME.getCell(RD, ResMap) << "\n"; } } @@ -949,7 +949,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) { void BT::visitUsesOf(unsigned Reg) { if (Trace) - dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n"; + dbgs() << "visiting uses of " << printReg(Reg, &ME.TRI) << "\n"; for (const MachineInstr &UseI : MRI.use_nodbg_instructions(Reg)) { if (!InstrExec.count(&UseI)) diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index a1f9e813cb2..cbf1b0dc040 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -173,7 +173,7 @@ namespace { raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) { OS << '{'; for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R)) - OS << ' ' << PrintReg(R, P.TRI); + OS << ' ' << printReg(R, P.TRI); OS << " }"; return OS; } @@ -2453,7 +2453,7 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI, return false; DEBUG({ - dbgs() << __func__ << " on reg: " << PrintReg(RD.Reg, &HRI, RD.Sub) + dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub) << ", MI: " << *MI; dbgs() << "Cell: " << RC << '\n'; dbgs() << "Expected bitfield size: " << Len << " bits, " @@ -3004,9 +3004,9 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) { DEBUG({ dbgs() << "Phis: {"; for (auto &I : Phis) { - dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi(" - << PrintReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() - << ',' << PrintReg(I.LR.Reg, HRI, I.LR.Sub) << ":b" + dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi(" + << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() + << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b" << I.LB->getNumber() << ')'; } dbgs() << " }\n"; @@ -3126,8 +3126,8 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) { for (unsigned i = 0, n = Groups.size(); i < n; ++i) { InstrGroup &G = Groups[i]; dbgs() << "Group[" << i << "] inp: " - << PrintReg(G.Inp.Reg, HRI, G.Inp.Sub) - << " out: " << PrintReg(G.Out.Reg, HRI, G.Out.Sub) << "\n"; + << printReg(G.Inp.Reg, HRI, G.Inp.Sub) + << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n"; for (unsigned j = 0, m = G.Ins.size(); j < m; ++j) dbgs() << " " << *G.Ins[j]; } diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp index 6d30191bec0..8297c474b8f 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp @@ -104,7 +104,7 @@ BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const { break; } #ifndef NDEBUG - dbgs() << PrintReg(Reg, &TRI, Sub) << " in reg class " + dbgs() << printReg(Reg, &TRI, Sub) << " in reg class " << TRI.getRegClassName(&RC) << '\n'; #endif llvm_unreachable("Unexpected register/subregister"); diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp index a63ab8fabb0..00db408b8ed 100644 --- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp @@ -531,7 +531,7 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, const HexagonBlockRanges::PrintRangeMap &P) { for (auto &I : P.Map) { const HexagonBlockRanges::RangeList &RL = I.second; - OS << PrintReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n"; + OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n"; } return OS; } diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp index 2235927d986..1e55c4b038e 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -422,7 +422,7 @@ namespace { LLVM_ATTRIBUTE_UNUSED raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &P) { if (P.Rs.Reg != 0) - OS << PrintReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); + OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); else OS << "noreg"; return OS; @@ -439,7 +439,7 @@ namespace { raw_ostream &operator<< (raw_ostream &OS, const PrintExpr &P) { OS << "## " << (P.Ex.Neg ? "- " : "+ "); if (P.Ex.Rs.Reg != 0) - OS << PrintReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub); + OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub); else OS << "__"; OS << " << " << P.Ex.S; @@ -468,7 +468,7 @@ namespace { const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); OS << "bb#" << MBB.getNumber() << ": "; if (ED.Rd.Reg != 0) - OS << PrintReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); + OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); else OS << "__"; OS << " = " << PrintExpr(ED.Expr, HRI); diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp index 7462b59c9e6..ed6c40deeba 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -88,7 +88,7 @@ namespace { : Reg(MO.getReg()), SubReg(MO.getSubReg()) {} void print(const TargetRegisterInfo *TRI = nullptr) const { - dbgs() << PrintReg(Reg, TRI, SubReg); + dbgs() << printReg(Reg, TRI, SubReg); } bool operator== (const Register &R) const { @@ -610,7 +610,7 @@ uint32_t LatticeCell::properties() const { void MachineConstPropagator::CellMap::print(raw_ostream &os, const TargetRegisterInfo &TRI) const { for (auto &I : Map) - dbgs() << " " << PrintReg(I.first, &TRI) << " -> " << I.second << '\n'; + dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n'; } #endif @@ -659,7 +659,7 @@ Bottomize: LatticeCell SrcC; bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC); DEBUG(dbgs() << " edge from BB#" << PBN << ": " - << PrintReg(UseR.Reg, &MCE.TRI, UseR.SubReg) + << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC << '\n'); Changed |= Eval ? DefC.meet(SrcC) : DefC.setBottom(); @@ -778,7 +778,7 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) { } void MachineConstPropagator::visitUsesOf(unsigned Reg) { - DEBUG(dbgs() << "Visiting uses of " << PrintReg(Reg, &MCE.TRI) + DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI) << Cells.get(Reg) << '\n'); for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) { // Do not process non-executable instructions. They can become exceutable @@ -2788,7 +2788,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI, HasUse = true; // PHIs can legitimately have "top" cells after propagation. if (!MI.isPHI() && !Inputs.has(R.Reg)) { - dbgs() << "Top " << PrintReg(R.Reg, &HRI, R.SubReg) + dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg) << " in MI: " << MI; continue; } @@ -2804,7 +2804,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI, if (!MO.isReg() || !MO.isUse() || MO.isImplicit()) continue; unsigned R = MO.getReg(); - dbgs() << PrintReg(R, &TRI) << ": " << Inputs.get(R) << "\n"; + dbgs() << printReg(R, &TRI) << ": " << Inputs.get(R) << "\n"; } } } diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index 2d9bd006c42..bec759a826d 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -144,7 +144,7 @@ namespace { const PrintFP &P) LLVM_ATTRIBUTE_UNUSED; raw_ostream &operator<<(raw_ostream &OS, const PrintFP &P) { OS << "{ SplitB:" << PrintMB(P.FP.SplitB) - << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI) + << ", PredR:" << printReg(P.FP.PredR, &P.TRI) << ", TrueB:" << PrintMB(P.FP.TrueB) << ", FalseB:" << PrintMB(P.FP.FalseB) << ", JoinB:" << PrintMB(P.FP.JoinB) << " }"; diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index 66cfab98ff0..51c3b784370 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -1137,8 +1137,8 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) { DEBUG(dbgs() << "compatible registers: (" << (Overlap ? "overlap" : "disjoint") << ")\n " - << PrintReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " - << PrintReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); + << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " + << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); if (R1.Sub || R2.Sub) return false; if (Overlap) diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index e13bbacd43d..ebb7add82e1 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -1371,7 +1371,7 @@ static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) { dbgs() << '{'; for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) { unsigned R = x; - dbgs() << ' ' << PrintReg(R, &TRI); + dbgs() << ' ' << printReg(R, &TRI); } dbgs() << " }"; } @@ -1393,7 +1393,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, DEBUG(dbgs() << "Initial CS registers: {"); for (unsigned i = 0, n = CSI.size(); i < n; ++i) { unsigned R = CSI[i].getReg(); - DEBUG(dbgs() << ' ' << PrintReg(R, TRI)); + DEBUG(dbgs() << ' ' << printReg(R, TRI)); for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) SRegs[*SR] = true; } @@ -1490,7 +1490,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, for (unsigned i = 0, n = CSI.size(); i < n; ++i) { int FI = CSI[i].getFrameIdx(); int Off = MFI.getObjectOffset(FI); - dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp"; + dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp"; if (Off >= 0) dbgs() << '+'; dbgs() << Off; @@ -1503,7 +1503,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, bool MissedReg = false; for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { unsigned R = x; - dbgs() << PrintReg(R, TRI) << ' '; + dbgs() << printReg(R, TRI) << ' '; MissedReg = true; } if (MissedReg) @@ -2207,7 +2207,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF); // The this-> is needed to unconfuse MSVC. unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC); - DEBUG(dbgs() << "Replacement reg:" << PrintReg(FoundR, &HRI) << '\n'); + DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI) << '\n'); if (FoundR == 0) continue; #ifndef NDEBUG diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp index 46d039af01e..09d3e6d4a15 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -180,7 +180,7 @@ namespace { raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) { OS << '{'; for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R)) - OS << ' ' << PrintReg(R, P.TRI); + OS << ' ' << printReg(R, P.TRI); OS << " }"; return OS; } @@ -419,7 +419,7 @@ namespace { for (OrderedRegisterList::const_iterator I = B; I != E; ++I) { if (I != B) OS << ", "; - OS << PrintReg(*I, P.TRI); + OS << printReg(*I, P.TRI); } OS << ')'; return OS; @@ -467,7 +467,7 @@ namespace { raw_ostream &operator<< (raw_ostream &OS, const PrintIFR &P) { unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; - OS << '(' << PrintReg(SrcR, P.TRI) << ',' << PrintReg(InsR, P.TRI) + OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI) << ",#" << P.IFR.Wdh << ",#" << P.IFR.Off << ')'; return OS; } @@ -568,7 +568,7 @@ void HexagonGenInsert::dump_map() const { using iterator = IFMapType::const_iterator; for (iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) { - dbgs() << " " << PrintReg(I->first, HRI) << ":\n"; + dbgs() << " " << printReg(I->first, HRI) << ":\n"; const IFListType &LL = I->second; for (unsigned i = 0, n = LL.size(); i < n; ++i) dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", " @@ -781,7 +781,7 @@ unsigned HexagonGenInsert::distance(MachineBasicBlock::const_iterator FromI, bool HexagonGenInsert::findRecordInsertForms(unsigned VR, OrderedRegisterList &AVs) { if (isDebug()) { - dbgs() << __func__ << ": " << PrintReg(VR, HRI) + dbgs() << __func__ << ": " << printReg(VR, HRI) << " AVs: " << PrintORL(AVs, HRI) << "\n"; } if (AVs.size() == 0) @@ -846,12 +846,12 @@ bool HexagonGenInsert::findRecordInsertForms(unsigned VR, } if (isDebug()) { - dbgs() << "Prefixes matching register " << PrintReg(VR, HRI) << "\n"; + dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n"; for (LRSMapType::iterator I = LM.begin(), E = LM.end(); I != E; ++I) { dbgs() << " L=" << I->first << ':'; const RSListType &LL = I->second; for (unsigned i = 0, n = LL.size(); i < n; ++i) - dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@" + dbgs() << " (" << printReg(LL[i].first, HRI) << ",@" << LL[i].second << ')'; dbgs() << '\n'; } @@ -898,8 +898,8 @@ bool HexagonGenInsert::findRecordInsertForms(unsigned VR, if (!isValidInsertForm(VR, SrcR, InsR, L, S)) continue; if (isDebug()) { - dbgs() << PrintReg(VR, HRI) << " = insert(" << PrintReg(SrcR, HRI) - << ',' << PrintReg(InsR, HRI) << ",#" << L << ",#" + dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI) + << ',' << printReg(InsR, HRI) << ",#" << L << ",#" << S << ")\n"; } IFRecordWithRegSet RR(IFRecord(SrcR, InsR, L, S), RegisterSet()); @@ -1524,7 +1524,7 @@ bool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) { for (RegisterOrdering::iterator I = CellOrd.begin(), E = CellOrd.end(); I != E; ++I) { unsigned VR = I->first, Pos = I->second; - dbgs() << PrintReg(VR, HRI) << " -> " << Pos << "\n"; + dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n"; } } diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp index 8ba46581b78..4eb24e07be4 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -74,7 +74,7 @@ namespace { raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) LLVM_ATTRIBUTE_UNUSED; raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) { - return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S); + return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S); } class HexagonGenPredicate : public MachineFunctionPass { @@ -223,12 +223,12 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) { void HexagonGenPredicate::processPredicateGPR(const Register &Reg) { DEBUG(dbgs() << __func__ << ": " - << PrintReg(Reg.R, TRI, Reg.S) << "\n"); + << printReg(Reg.R, TRI, Reg.S) << "\n"); using use_iterator = MachineRegisterInfo::use_iterator; use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end(); if (I == E) { - DEBUG(dbgs() << "Dead reg: " << PrintReg(Reg.R, TRI, Reg.S) << '\n'); + DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n'); MachineInstr *DefI = MRI->getVRegDef(Reg.R); DefI->eraseFromParent(); return; diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 7250f48b673..5ca8b0f30e0 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -357,7 +357,7 @@ namespace { } void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const { - if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); } + if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); } if (isImm()) { OS << Contents.ImmVal; } } }; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 3a4ebe08e82..3c0b3061688 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -830,8 +830,8 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, #ifndef NDEBUG // Show the invalid registers to ease debugging. dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber() - << ": " << PrintReg(DestReg, &HRI) - << " = " << PrintReg(SrcReg, &HRI) << '\n'; + << ": " << printReg(DestReg, &HRI) + << " = " << printReg(SrcReg, &HRI) << '\n'; #endif llvm_unreachable("Unimplemented"); } diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp index 1e908ab157b..75d6750322b 100644 --- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -136,7 +136,7 @@ LLVM_DUMP_METHOD void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os, const USet &Part, const TargetRegisterInfo &TRI) { dbgs() << '{'; for (auto I : Part) - dbgs() << ' ' << PrintReg(I, &TRI); + dbgs() << ' ' << printReg(I, &TRI); dbgs() << " }"; } #endif @@ -244,7 +244,7 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) { if (FixedRegs[x]) continue; unsigned R = TargetRegisterInfo::index2VirtReg(x); - DEBUG(dbgs() << PrintReg(R, TRI) << " ~~"); + DEBUG(dbgs() << printReg(R, TRI) << " ~~"); USet &Asc = AssocMap[R]; for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end(); U != Z; ++U) { @@ -267,7 +267,7 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) { unsigned u = TargetRegisterInfo::virtReg2Index(T); if (FixedRegs[u]) continue; - DEBUG(dbgs() << ' ' << PrintReg(T, TRI)); + DEBUG(dbgs() << ' ' << printReg(T, TRI)); Asc.insert(T); // Make it symmetric. AssocMap[T].insert(R); @@ -1122,8 +1122,8 @@ bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) { unsigned LoR = MRI->createVirtualRegister(IntRC); unsigned HiR = MRI->createVirtualRegister(IntRC); - DEBUG(dbgs() << "Created mapping: " << PrintReg(DR, TRI) << " -> " - << PrintReg(HiR, TRI) << ':' << PrintReg(LoR, TRI) << '\n'); + DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> " + << printReg(HiR, TRI) << ':' << printReg(LoR, TRI) << '\n'); PairMap.insert(std::make_pair(DR, UUPair(LoR, HiR))); } diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.cpp b/llvm/lib/Target/Hexagon/RDFLiveness.cpp index fed5a66b340..740cd11136b 100644 --- a/llvm/lib/Target/Hexagon/RDFLiveness.cpp +++ b/llvm/lib/Target/Hexagon/RDFLiveness.cpp @@ -62,7 +62,7 @@ namespace rdf { raw_ostream &operator<< (raw_ostream &OS, const Print<Liveness::RefMap> &P) { OS << '{'; for (auto &I : P.Obj) { - OS << ' ' << PrintReg(I.first, &P.G.getTRI()) << '{'; + OS << ' ' << printReg(I.first, &P.G.getTRI()) << '{'; for (auto J = I.second.begin(), E = I.second.end(); J != E; ) { OS << Print<NodeId>(J->first, P.G) << PrintLaneMaskOpt(J->second); if (++J != E) diff --git a/llvm/lib/Target/Hexagon/RDFRegisters.cpp b/llvm/lib/Target/Hexagon/RDFRegisters.cpp index 429add94662..9408c5dc395 100644 --- a/llvm/lib/Target/Hexagon/RDFRegisters.cpp +++ b/llvm/lib/Target/Hexagon/RDFRegisters.cpp @@ -365,7 +365,7 @@ RegisterRef RegisterAggr::makeRegRef() const { void RegisterAggr::print(raw_ostream &OS) const { OS << '{'; for (int U = Units.find_first(); U >= 0; U = Units.find_next(U)) - OS << ' ' << PrintRegUnit(U, &PRI.getTRI()); + OS << ' ' << printRegUnit(U, &PRI.getTRI()); OS << " }"; } |
