diff options
Diffstat (limited to 'llvm/lib/Target')
39 files changed, 181 insertions, 30 deletions
diff --git a/llvm/lib/Target/MRegisterInfo.cpp b/llvm/lib/Target/MRegisterInfo.cpp index 6f358152638..7c1028bc323 100644 --- a/llvm/lib/Target/MRegisterInfo.cpp +++ b/llvm/lib/Target/MRegisterInfo.cpp @@ -13,6 +13,8 @@ #include "llvm/Target/MRegisterInfo.h" +namespace llvm { + MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR, regclass_iterator RCB, regclass_iterator RCE, int CFSO, int CFDO) @@ -41,3 +43,5 @@ MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR, MRegisterInfo::~MRegisterInfo() { delete[] PhysRegClasses; } + +} // End llvm namespace diff --git a/llvm/lib/Target/Sparc/EmitAssembly.cpp b/llvm/lib/Target/Sparc/EmitAssembly.cpp index 25034177da4..6af9836e29b 100644 --- a/llvm/lib/Target/Sparc/EmitAssembly.cpp +++ b/llvm/lib/Target/Sparc/EmitAssembly.cpp @@ -33,6 +33,8 @@ #include "SparcInternals.h" #include <string> +namespace llvm { + namespace { Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); @@ -877,12 +879,13 @@ SparcFunctionAsmPrinter::emitFunction(const Function &F) } // End anonymous namespace +namespace llvm { + Pass *UltraSparc::getFunctionAsmPrinterPass(std::ostream &Out) { return new SparcFunctionAsmPrinter(Out, *this); } - - +} // End llvm namespace //===----------------------------------------------------------------------===// @@ -954,3 +957,5 @@ void SparcModuleAsmPrinter::emitGlobals(const Module &M) { Pass *UltraSparc::getModuleAsmPrinterPass(std::ostream &Out) { return new SparcModuleAsmPrinter(Out, *this); } + +} // End llvm namespace diff --git a/llvm/lib/Target/Sparc/EmitBytecodeToAssembly.cpp b/llvm/lib/Target/Sparc/EmitBytecodeToAssembly.cpp index 2c45021f007..a603e94b819 100644 --- a/llvm/lib/Target/Sparc/EmitBytecodeToAssembly.cpp +++ b/llvm/lib/Target/Sparc/EmitBytecodeToAssembly.cpp @@ -18,6 +18,8 @@ #include "llvm/Bytecode/Writer.h" #include <iostream> +namespace llvm { + using std::ostream; namespace { @@ -113,3 +115,5 @@ namespace { Pass *UltraSparc::getBytecodeAsmPrinterPass(std::ostream &Out) { return new SparcBytecodeWriter(Out); } + +} // End llvm namespace diff --git a/llvm/lib/Target/Sparc/MappingInfo.cpp b/llvm/lib/Target/Sparc/MappingInfo.cpp index db03f13b976..2afde6bdf59 100644 --- a/llvm/lib/Target/Sparc/MappingInfo.cpp +++ b/llvm/lib/Target/Sparc/MappingInfo.cpp @@ -49,6 +49,8 @@ #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "Support/StringExtras.h" +namespace llvm { + namespace { class MappingInfoAsmPrinter : public FunctionPass { std::ostream &Out; @@ -293,3 +295,5 @@ bool MappingInfoAsmPrinter::doFinalization (Module &M) { return false; } +} // End llvm namespace + diff --git a/llvm/lib/Target/Sparc/MappingInfo.h b/llvm/lib/Target/Sparc/MappingInfo.h index f86e2b42b7a..6af116a6da2 100644 --- a/llvm/lib/Target/Sparc/MappingInfo.h +++ b/llvm/lib/Target/Sparc/MappingInfo.h @@ -18,6 +18,9 @@ #include <iosfwd> #include <vector> #include <string> + +namespace llvm { + class Pass; Pass *getMappingInfoAsmPrinterPass(std::ostream &out); @@ -41,4 +44,6 @@ public: } }; +} // End llvm namespace + #endif diff --git a/llvm/lib/Target/Sparc/PeepholeOpts.cpp b/llvm/lib/Target/Sparc/PeepholeOpts.cpp index 83081b71203..9713a02d95e 100644 --- a/llvm/lib/Target/Sparc/PeepholeOpts.cpp +++ b/llvm/lib/Target/Sparc/PeepholeOpts.cpp @@ -20,6 +20,8 @@ #include "llvm/BasicBlock.h" #include "llvm/Pass.h" +namespace llvm { + //************************* Internal Functions *****************************/ static inline void @@ -163,3 +165,5 @@ bool PeepholeOpts::runOnBasicBlock(BasicBlock &BB) { FunctionPass* createPeepholeOptsPass(const TargetMachine &TM) { return new PeepholeOpts(TM); } + +} // End llvm namespace diff --git a/llvm/lib/Target/Sparc/PreSelection.cpp b/llvm/lib/Target/Sparc/PreSelection.cpp index 9078dc13b1e..205ecd3145c 100644 --- a/llvm/lib/Target/Sparc/PreSelection.cpp +++ b/llvm/lib/Target/Sparc/PreSelection.cpp @@ -29,6 +29,8 @@ #include "llvm/Transforms/Scalar.h" #include <algorithm> +namespace llvm { + namespace { //===--------------------------------------------------------------------===// @@ -71,6 +73,7 @@ namespace { "Specialize LLVM code for a target machine" createPreselectionPass); #endif + } // end anonymous namespace @@ -236,7 +239,6 @@ void PreSelection::visitCallInst(CallInst &I) { visitOperands(I, (/*firstOp=*/ I.getCalledFunction()? 1 : 0)); } - //===----------------------------------------------------------------------===// // createPreSelectionPass - Public entrypoint for pre-selection pass // and this file as a whole... @@ -244,3 +246,5 @@ void PreSelection::visitCallInst(CallInst &I) { FunctionPass* createPreSelectionPass(const TargetMachine &TM) { return new PreSelection(TM); } + +} // End llvm namespace diff --git a/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp b/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp index ff7bd7d0269..555b6b14fe7 100644 --- a/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp +++ b/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp @@ -27,6 +27,8 @@ #include "llvm/DerivedTypes.h" #include "llvm/Intrinsics.h" +namespace llvm { + namespace { struct InsertPrologEpilogCode : public MachineFunctionPass { const char *getPassName() const { return "Sparc Prolog/Epilog Inserter"; } @@ -177,3 +179,5 @@ void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF) FunctionPass *UltraSparc::getPrologEpilogInsertionPass() { return new InsertPrologEpilogCode(); } + +} // End llvm namespace diff --git a/llvm/lib/Target/Sparc/Sparc.burg.in b/llvm/lib/Target/Sparc/Sparc.burg.in index a5bc98fa899..38dc2439ce8 100644 --- a/llvm/lib/Target/Sparc/Sparc.burg.in +++ b/llvm/lib/Target/Sparc/Sparc.burg.in @@ -11,7 +11,7 @@ Xinclude <cstdio> Xinclude <llvm/CodeGen/InstrForest.h> -typedef InstrTreeNode* NODEPTR_TYPE; +typedef llvm::InstrTreeNode* NODEPTR_TYPE; Xdefine OP_LABEL(p) ((p)->opLabel) Xdefine LEFT_CHILD(p) ((p)->LeftChild) Xdefine RIGHT_CHILD(p) ((p)->RightChild) diff --git a/llvm/lib/Target/Sparc/Sparc.cpp b/llvm/lib/Target/Sparc/Sparc.cpp index d20fc758d0d..73f2fd81395 100644 --- a/llvm/lib/Target/Sparc/Sparc.cpp +++ b/llvm/lib/Target/Sparc/Sparc.cpp @@ -27,6 +27,8 @@ #include "llvm/Target/TargetMachineImpls.h" #include "Support/CommandLine.h" +namespace llvm { + static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */ // Build the MachineInstruction Description Array... const TargetInstrDescriptor SparcMachineInstrDesc[] = { @@ -267,3 +269,5 @@ bool UltraSparc::addPassesToJITCompile(FunctionPassManager &PM) { return false; // success! } + +} // End llvm namespace diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index d92e3be9ca2..11b0c7beab5 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -23,6 +23,8 @@ #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +namespace llvm { + static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*) static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR @@ -792,3 +794,5 @@ UltraSparcInstrInfo::CreateZeroExtensionInstructions( CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal, destVal, numLowBits, mvec, mcfi); } + +} // End llvm namespace diff --git a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp index b377658b9c8..21e884be8e1 100644 --- a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp @@ -32,6 +32,8 @@ #include <algorithm> #include <cmath> +namespace llvm { + static inline void Add3OperandInstr(unsigned Opcode, InstructionNode* Node, std::vector<MachineInstr*>& mvec) { mvec.push_back(BuildMI(Opcode, 3).addReg(Node->leftChild()->getValue()) @@ -1390,12 +1392,12 @@ AllUsesAreBranches(const Instruction* setccI) // instead of a regular call. If not that kind of intrinsic, do nothing. // Returns true if code was generated, otherwise false. // -bool CodeGenIntrinsic(LLVMIntrinsic::ID iid, CallInst &callInstr, +bool CodeGenIntrinsic(Intrinsic::ID iid, CallInst &callInstr, TargetMachine &target, std::vector<MachineInstr*>& mvec) { switch (iid) { - case LLVMIntrinsic::va_start: { + case Intrinsic::va_start: { // Get the address of the first incoming vararg argument on the stack bool ignore; Function* func = cast<Function>(callInstr.getParent()->getParent()); @@ -1409,10 +1411,10 @@ bool CodeGenIntrinsic(LLVMIntrinsic::ID iid, CallInst &callInstr, return true; } - case LLVMIntrinsic::va_end: + case Intrinsic::va_end: return true; // no-op on Sparc - case LLVMIntrinsic::va_copy: + case Intrinsic::va_copy: // Simple copy of current va_list (arg1) to new va_list (result) mvec.push_back(BuildMI(V9::ORr, 3). addMReg(target.getRegInfo().getZeroRegNum()). @@ -1420,8 +1422,8 @@ bool CodeGenIntrinsic(LLVMIntrinsic::ID iid, CallInst &callInstr, addRegDef(&callInstr)); return true; - case LLVMIntrinsic::sigsetjmp: - case LLVMIntrinsic::setjmp: { + case Intrinsic::sigsetjmp: + case Intrinsic::setjmp: { // act as if we return 0 unsigned g0 = target.getRegInfo().getZeroRegNum(); mvec.push_back(BuildMI(V9::ORr,3).addMReg(g0).addMReg(g0) @@ -1429,8 +1431,8 @@ bool CodeGenIntrinsic(LLVMIntrinsic::ID iid, CallInst &callInstr, return true; } - case LLVMIntrinsic::siglongjmp: - case LLVMIntrinsic::longjmp: { + case Intrinsic::siglongjmp: + case Intrinsic::longjmp: { // call abort() Module* M = callInstr.getParent()->getParent()->getParent(); const FunctionType *voidvoidFuncTy = @@ -2474,8 +2476,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, // sequence (e.g., va_start). Indirect calls cannot be special. // bool specialIntrinsic = false; - LLVMIntrinsic::ID iid; - if (calledFunc && (iid=(LLVMIntrinsic::ID)calledFunc->getIntrinsicID())) + Intrinsic::ID iid; + if (calledFunc && (iid=(Intrinsic::ID)calledFunc->getIntrinsicID())) specialIntrinsic = CodeGenIntrinsic(iid, *callInstr, target, mvec); // If not, generate the normal call sequence for the function. @@ -2929,3 +2931,5 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, } } } + +} diff --git a/llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h b/llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h index d49863c1c84..b69c5c2b6e4 100644 --- a/llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h +++ b/llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h @@ -17,6 +17,8 @@ #include "llvm/DerivedTypes.h" #include "SparcInternals.h" +namespace llvm { + // Choose load instruction opcode based on type of value inline MachineOpCode ChooseLoadInstruction(const Type *DestTy) @@ -220,4 +222,6 @@ convertOpcodeFromRegToImm(unsigned Opcode) { } } +} // End llvm namespace + #endif diff --git a/llvm/lib/Target/Sparc/SparcInternals.h b/llvm/lib/Target/Sparc/SparcInternals.h index 4d0a48e4d5d..5e5f155e399 100644 --- a/llvm/lib/Target/Sparc/SparcInternals.h +++ b/llvm/lib/Target/Sparc/SparcInternals.h @@ -25,6 +25,8 @@ #include "SparcRegClassInfo.h" #include "Config/sys/types.h" +namespace llvm { + class LiveRange; class UltraSparc; class Pass; @@ -693,4 +695,6 @@ public: Pass* getBytecodeAsmPrinterPass(std::ostream &Out); }; +} // End llvm namespace + #endif diff --git a/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp b/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp index d6de5f9c0df..564e59cd70e 100644 --- a/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp @@ -17,6 +17,8 @@ #include "../../CodeGen/RegAlloc/RegAllocCommon.h" // FIXME! #include "../../CodeGen/RegAlloc/IGNode.h" // FIXME! +namespace llvm { + //----------------------------------------------------------------------------- // Int Register Class - method for coloring a node in the interference graph. // @@ -390,3 +392,5 @@ int SparcFloatRegClass::findFloatColor(const LiveRange *LR, return -1; } + +} // End llvm namespace diff --git a/llvm/lib/Target/Sparc/SparcRegClassInfo.h b/llvm/lib/Target/Sparc/SparcRegClassInfo.h index 321ce60ab0f..cc492e77c72 100644 --- a/llvm/lib/Target/Sparc/SparcRegClassInfo.h +++ b/llvm/lib/Target/Sparc/SparcRegClassInfo.h @@ -16,6 +16,8 @@ #include "llvm/Target/TargetRegInfo.h" +namespace llvm { + //----------------------------------------------------------------------------- // Integer Register Class //----------------------------------------------------------------------------- @@ -217,4 +219,6 @@ struct SparcSpecialRegClass : public TargetRegClassInfo { const char * const getRegName(unsigned reg) const; }; +} // End llvm namespace + #endif diff --git a/llvm/lib/Target/Sparc/SparcRegInfo.cpp b/llvm/lib/Target/Sparc/SparcRegInfo.cpp index 84dc92e246d..5edbbe06470 100644 --- a/llvm/lib/Target/Sparc/SparcRegInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegInfo.cpp @@ -27,6 +27,8 @@ #include "llvm/Function.h" #include "llvm/DerivedTypes.h" +namespace llvm { + enum { BadRegClass = ~0 }; @@ -967,3 +969,5 @@ void UltraSparcRegInfo::printReg(const LiveRange *LR) const { std::cerr << "+" << getUnifiedRegName(uRegName+1); std::cerr << "]\n"; } + +} // End llvm namespace diff --git a/llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp b/llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp index d60d9151c1c..c50dca55e78 100644 --- a/llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp +++ b/llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp @@ -38,6 +38,8 @@ #include "SparcV9CodeEmitter.h" #include "Config/alloca.h" +namespace llvm { + namespace { Statistic<> OverwrittenCalls("call-ovwr", "Number of over-written calls"); Statistic<> UnmodifiedCalls("call-skip", "Number of unmodified calls"); @@ -443,7 +445,6 @@ uint64_t JITResolver::emitStubForFunction(Function *F) { return (intptr_t)MCE.finishFunctionStub(*F)+4; /* 1 instr past the restore */ } - SparcV9CodeEmitter::SparcV9CodeEmitter(TargetMachine &tm, MachineCodeEmitter &M): TM(tm), MCE(M) { @@ -809,4 +810,6 @@ void* SparcV9CodeEmitter::getGlobalAddress(GlobalValue *V, MachineInstr &MI, } } +} // End llvm namespace + #include "SparcV9CodeEmitter.inc" diff --git a/llvm/lib/Target/Sparc/SparcV9CodeEmitter.h b/llvm/lib/Target/Sparc/SparcV9CodeEmitter.h index 7e19c44ce03..d21345ec041 100644 --- a/llvm/lib/Target/Sparc/SparcV9CodeEmitter.h +++ b/llvm/lib/Target/Sparc/SparcV9CodeEmitter.h @@ -19,6 +19,8 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/Target/TargetMachine.h" +namespace llvm { + class GlobalValue; class MachineInstr; class MachineOperand; @@ -81,4 +83,6 @@ private: }; +} // End llvm namespace + #endif diff --git a/llvm/lib/Target/Sparc/StackSlots.cpp b/llvm/lib/Target/Sparc/StackSlots.cpp index 551dd92b495..5fd0ba19271 100644 --- a/llvm/lib/Target/Sparc/StackSlots.cpp +++ b/llvm/lib/Target/Sparc/StackSlots.cpp @@ -20,6 +20,8 @@ #include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" +namespace llvm { + namespace { class StackSlots : public MachineFunctionPass { const TargetMachine &Target; @@ -48,3 +50,5 @@ namespace { Pass *createStackSlotsPass(const TargetMachine &Target) { return new StackSlots(Target); } + +} // End llvm namespace diff --git a/llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp b/llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp index fd03ad69d67..7d8ea05066c 100644 --- a/llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp +++ b/llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp @@ -13,6 +13,8 @@ #include "SparcInternals.h" +using namespace llvm; + /*--------------------------------------------------------------------------- Scheduling guidelines for SPARC IIi: diff --git a/llvm/lib/Target/TargetData.cpp b/llvm/lib/Target/TargetData.cpp index a377fd0d7f9..ed6936dd122 100644 --- a/llvm/lib/Target/TargetData.cpp +++ b/llvm/lib/Target/TargetData.cpp @@ -22,13 +22,14 @@ #include "llvm/DerivedTypes.h" #include "llvm/Constants.h" +namespace llvm { + // Handle the Pass registration stuff necessary to use TargetData's. namespace { // Register the default SparcV9 implementation... RegisterPass<TargetData> X("targetdata", "Target Data Layout"); } - static inline void getTypeInfo(const Type *Ty, const TargetData *TD, uint64_t &Size, unsigned char &Alignment); @@ -221,3 +222,5 @@ uint64_t TargetData::getIndexedOffset(const Type *ptrTy, return Result; } + +} // End llvm namespace diff --git a/llvm/lib/Target/TargetInstrInfo.cpp b/llvm/lib/Target/TargetInstrInfo.cpp index f377d67b66f..0f9015f8a60 100644 --- a/llvm/lib/Target/TargetInstrInfo.cpp +++ b/llvm/lib/Target/TargetInstrInfo.cpp @@ -15,6 +15,8 @@ #include "llvm/Constant.h" #include "llvm/DerivedTypes.h" +namespace llvm { + // External object describing the machine instructions // Initialized only when the TargetMachine class is created // and reset when that class is destroyed. @@ -59,3 +61,5 @@ bool TargetInstrInfo::ConstantTypeMustBeLoaded(const Constant* CV) const { assert(CV->getType()->isPrimitiveType() || isa<PointerType>(CV->getType())); return !(CV->getType()->isIntegral() || isa<PointerType>(CV->getType())); } + +} // End llvm namespace diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp index b7c1b342e12..e7630b4ab34 100644 --- a/llvm/lib/Target/TargetMachine.cpp +++ b/llvm/lib/Target/TargetMachine.cpp @@ -16,6 +16,8 @@ #include "llvm/Target/TargetCacheInfo.h" #include "llvm/Type.h" +namespace llvm { + //--------------------------------------------------------------------------- // class TargetMachine // @@ -49,3 +51,5 @@ void TargetCacheInfo::Initialize() { cacheSizes.push_back(1 << 15); cacheSizes.push_back(1 << 20); cacheAssoc.push_back(1); cacheAssoc.push_back(4); } + +} // End llvm namespace diff --git a/llvm/lib/Target/TargetSchedInfo.cpp b/llvm/lib/Target/TargetSchedInfo.cpp index 0dbde45c38e..f33223c43a6 100644 --- a/llvm/lib/Target/TargetSchedInfo.cpp +++ b/llvm/lib/Target/TargetSchedInfo.cpp @@ -15,6 +15,8 @@ #include "llvm/Target/TargetSchedInfo.h" #include "llvm/Target/TargetMachine.h" +namespace llvm { + resourceId_t MachineResource::nextId = 0; // Check if fromRVec and toRVec have *any* common entries. @@ -249,3 +251,5 @@ void InstrRUsage::addUsageDelta(const InstrRUsageDelta &delta) { assert(r >= 0 && "Resource to remove was unused in cycle c!"); } } + +} // End llvm namespace diff --git a/llvm/lib/Target/X86/FloatingPoint.cpp b/llvm/lib/Target/X86/FloatingPoint.cpp index 07e58ba171c..5c6e6ebfdde 100644 --- a/llvm/lib/Target/X86/FloatingPoint.cpp +++ b/llvm/lib/Target/X86/FloatingPoint.cpp @@ -25,6 +25,8 @@ #include <algorithm> #include <iostream> +namespace llvm { + namespace { Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted"); Statistic<> NumFP ("x86-codegen", "Number of floating point instructions"); @@ -70,7 +72,7 @@ namespace { // getSTReg - Return the X86::ST(i) register which contains the specified // FP<RegNo> register unsigned getSTReg(unsigned RegNo) const { - return StackTop - 1 - getSlot(RegNo) + X86::ST0; + return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; } // pushReg - Push the specifiex FP<n> register onto the stack @@ -598,3 +600,5 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { I = MBB->erase(I)-1; // Remove the pseudo instruction } + +} // End llvm namespace diff --git a/llvm/lib/Target/X86/InstSelectPattern.cpp b/llvm/lib/Target/X86/InstSelectPattern.cpp index 434ceee91c6..e5182945646 100644 --- a/llvm/lib/Target/X86/InstSelectPattern.cpp +++ b/llvm/lib/Target/X86/InstSelectPattern.cpp @@ -28,6 +28,8 @@ // Include the generated instruction selector... #include "X86GenInstrSelector.inc" +namespace llvm { + namespace { struct ISel : public FunctionPass, SelectionDAGTargetBuilder { TargetMachine &TM; @@ -114,7 +116,6 @@ void ISel::expandCall(SelectionDAG &SD, CallInst &CI) { assert(0 && "ISel::expandCall not implemented!"); } - /// createX86PatternInstructionSelector - This pass converts an LLVM function /// into a machine code representation using pattern matching and a machine /// description file. @@ -122,3 +123,5 @@ void ISel::expandCall(SelectionDAG &SD, CallInst &CI) { FunctionPass *createX86PatternInstructionSelector(TargetMachine &TM) { return new ISel(TM); } + +} // End llvm namespace diff --git a/llvm/lib/Target/X86/InstSelectSimple.cpp b/llvm/lib/Target/X86/InstSelectSimple.cpp index 1242545d83a..de341c477dc 100644 --- a/llvm/lib/Target/X86/InstSelectSimple.cpp +++ b/llvm/lib/Target/X86/InstSelectSimple.cpp @@ -29,6 +29,8 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Support/InstVisitor.h" +namespace llvm { + /// BMI - A special BuildMI variant that takes an iterator to insert the /// instruction at as well as a basic block. This is the version for when you /// have a destination register in mind. @@ -138,7 +140,7 @@ namespace { void doCall(const ValueRecord &Ret, MachineInstr *CallMI, const std::vector<ValueRecord> &Args); void visitCallInst(CallInst &I); - void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I); + void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I); // Arithmetic operators void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass); @@ -1045,7 +1047,7 @@ void ISel::visitCallInst(CallInst &CI) { MachineInstr *TheCall; if (Function *F = CI.getCalledFunction()) { // Is it an intrinsic function call? - if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) { + if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) { visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here return; } @@ -1066,29 +1068,29 @@ void ISel::visitCallInst(CallInst &CI) { } -void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) { +void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) { unsigned TmpReg1, TmpReg2; switch (ID) { - case LLVMIntrinsic::va_start: + case Intrinsic::va_start: // Get the address of the first vararg value... TmpReg1 = getReg(CI); addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex); return; - case LLVMIntrinsic::va_copy: + case Intrinsic::va_copy: TmpReg1 = getReg(CI); TmpReg2 = getReg(CI.getOperand(1)); BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2); return; - case LLVMIntrinsic::va_end: return; // Noop on X86 + case Intrinsic::va_end: return; // Noop on X86 - case LLVMIntrinsic::longjmp: - case LLVMIntrinsic::siglongjmp: + case Intrinsic::longjmp: + case Intrinsic::siglongjmp: BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("abort", true); return; - case LLVMIntrinsic::setjmp: - case LLVMIntrinsic::sigsetjmp: + case Intrinsic::setjmp: + case Intrinsic::sigsetjmp: // Setjmp always returns zero... BuildMI(BB, X86::MOVir32, 1, getReg(CI)).addZImm(0); return; @@ -2127,7 +2129,6 @@ void ISel::visitFreeInst(FreeInst &I) { doCall(ValueRecord(0, Type::VoidTy), TheCall, Args); } - /// createX86SimpleInstructionSelector - This pass converts an LLVM function /// into a machine code representation is a very simple peep-hole fashion. The /// generated code sucks but the implementation is nice and simple. @@ -2135,3 +2136,5 @@ void ISel::visitFreeInst(FreeInst &I) { FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM) { return new ISel(TM); } + +} // End llvm namespace diff --git a/llvm/lib/Target/X86/PeepholeOptimizer.cpp b/llvm/lib/Target/X86/PeepholeOptimizer.cpp index fbc84f7e871..2f3280a4bbb 100644 --- a/llvm/lib/Target/X86/PeepholeOptimizer.cpp +++ b/llvm/lib/Target/X86/PeepholeOptimizer.cpp @@ -15,6 +15,8 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +namespace llvm { + namespace { struct PH : public MachineFunctionPass { virtual bool runOnMachineFunction(MachineFunction &MF); @@ -131,3 +133,5 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB, return false; } } + +} // End llvm namespace diff --git a/llvm/lib/Target/X86/Printer.cpp b/llvm/lib/Target/X86/Printer.cpp index 3d073f77c65..292a465e725 100644 --- a/llvm/lib/Target/X86/Printer.cpp +++ b/llvm/lib/Target/X86/Printer.cpp @@ -29,6 +29,8 @@ #include "Support/StringExtras.h" #include "Support/CommandLine.h" +namespace llvm { + namespace { Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); @@ -960,3 +962,5 @@ bool Printer::doFinalization(Module &M) { delete Mang; return false; // success } + +} // End llvm namespace diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h index 01041f8d3a8..5cf897fa715 100644 --- a/llvm/lib/Target/X86/X86.h +++ b/llvm/lib/Target/X86/X86.h @@ -16,6 +16,9 @@ #define TARGET_X86_H #include <iosfwd> + +namespace llvm { + class TargetMachine; class FunctionPass; @@ -58,6 +61,8 @@ FunctionPass *createEmitX86CodeToMemory(); // Defines symbolic names for X86 registers. This defines a mapping from // register name to register number. // +} // End llvm namespace + #include "X86GenRegisterNames.inc" // Defines symbolic names for the X86 instructions. diff --git a/llvm/lib/Target/X86/X86CodeEmitter.cpp b/llvm/lib/Target/X86/X86CodeEmitter.cpp index f49fde58d20..e24e2904b51 100644 --- a/llvm/lib/Target/X86/X86CodeEmitter.cpp +++ b/llvm/lib/Target/X86/X86CodeEmitter.cpp @@ -24,6 +24,8 @@ #include "Support/Statistic.h" #include "Config/alloca.h" +namespace llvm { + namespace { Statistic<> NumEmitted("x86-emitter", "Number of machine instructions emitted"); @@ -589,3 +591,5 @@ void Emitter::emitInstruction(MachineInstr &MI) { break; } } + +} // End llvm namespace diff --git a/llvm/lib/Target/X86/X86InstrBuilder.h b/llvm/lib/Target/X86/X86InstrBuilder.h index a6d65d47495..a5643bdbfb6 100644 --- a/llvm/lib/Target/X86/X86InstrBuilder.h +++ b/llvm/lib/Target/X86/X86InstrBuilder.h @@ -26,6 +26,8 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" +namespace llvm { + /// addDirectMem - This function is used to add a direct memory reference to the /// current instruction -- that is, a dereference of an address in a register, /// with no scale, index or displacement. An example is: DWORD PTR [EAX]. @@ -69,4 +71,6 @@ addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addSImm(Offset); } +} // End llvm namespace + #endif diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 012ceadff0b..681bf023d99 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -17,6 +17,8 @@ #include "X86GenInstrInfo.inc" +using namespace llvm; + X86InstrInfo::X86InstrInfo() : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) { } diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index 26b2618a01f..2bf82d16c63 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -17,6 +17,8 @@ #include "llvm/Target/TargetInstrInfo.h" #include "X86RegisterInfo.h" +namespace llvm { + /// X86II - This namespace holds all of the target specific flags that /// instruction info tracks. /// @@ -181,4 +183,6 @@ public: } }; +} // End llvm namespace + #endif diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index fd8a615e316..0e8b889ad8d 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -25,6 +25,8 @@ #include "llvm/Target/TargetFrameInfo.h" #include "Support/CommandLine.h" +namespace llvm { + namespace { cl::opt<bool> NoFPElim("disable-fp-elim", @@ -253,8 +255,12 @@ int X86RegisterInfo::emitEpilogue(MachineFunction &MF, return MBB.size() - oldSize; } +} // End llvm namespace + #include "X86GenRegisterInfo.inc" +namespace llvm { + const TargetRegisterClass* X86RegisterInfo::getRegClassForType(const Type* Ty) const { switch (Ty->getPrimitiveID()) { @@ -274,3 +280,5 @@ X86RegisterInfo::getRegClassForType(const Type* Ty) const { case Type::DoubleTyID: return &RFPInstance; } } + +} // End llvm namespace diff --git a/llvm/lib/Target/X86/X86RegisterInfo.h b/llvm/lib/Target/X86/X86RegisterInfo.h index 0db8e18bee1..77a8a1a4053 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.h +++ b/llvm/lib/Target/X86/X86RegisterInfo.h @@ -16,10 +16,12 @@ #include "llvm/Target/MRegisterInfo.h" -class Type; +class llvm::Type; #include "X86GenRegisterInfo.h.inc" +namespace llvm { + struct X86RegisterInfo : public X86GenRegisterInfo { X86RegisterInfo(); const TargetRegisterClass* getRegClassForType(const Type* Ty) const; @@ -52,4 +54,6 @@ struct X86RegisterInfo : public X86GenRegisterInfo { int emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; }; +} // End llvm namespace + #endif diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index 954d4f4ced6..31eb4bd61c2 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -22,6 +22,8 @@ #include "Support/CommandLine.h" #include "Support/Statistic.h" +namespace llvm { + namespace { cl::opt<bool> PrintCode("print-machineinstrs", cl::desc("Print generated machine code")); @@ -153,3 +155,5 @@ void X86TargetMachine::replaceMachineCodeForFunction (void *Old, void *New) { int32_t OldAddr = (intptr_t) OldWord; *OldWord = NewAddr - OldAddr - 4; // Emit PC-relative addr of New code. } + +} // End llvm namespace diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h index 5581da4d818..12f5c0e6a22 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.h +++ b/llvm/lib/Target/X86/X86TargetMachine.h @@ -19,6 +19,8 @@ #include "llvm/PassManager.h" #include "X86InstrInfo.h" +namespace llvm { + class X86TargetMachine : public TargetMachine { X86InstrInfo InstrInfo; TargetFrameInfo FrameInfo; @@ -55,4 +57,6 @@ public: virtual void replaceMachineCodeForFunction (void *Old, void *New); }; +} // End llvm namespace + #endif |
