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-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp2
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp2
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp2
-rw-r--r--llvm/lib/Target/ARM/ARMAsmPrinter.cpp8
-rw-r--r--llvm/lib/Target/ARM/ARMConstantIslandPass.cpp4
-rw-r--r--llvm/lib/Target/ARM/ARMConstantPoolValue.cpp2
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp2
-rw-r--r--llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp2
-rw-r--r--llvm/lib/Target/BPF/BPFMCInstLower.cpp2
-rw-r--r--llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp2
-rw-r--r--llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp4
-rw-r--r--llvm/lib/Target/Lanai/LanaiMCInstLower.cpp2
-rw-r--r--llvm/lib/Target/MSP430/MSP430MCInstLower.cpp2
-rw-r--r--llvm/lib/Target/Mips/MipsConstantIslandPass.cpp16
-rw-r--r--llvm/lib/Target/PowerPC/PPCMCInstLower.cpp2
-rw-r--r--llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp53
-rw-r--r--llvm/lib/Target/X86/X86MCInstLower.cpp2
17 files changed, 58 insertions, 51 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index c9c44bf9d80..631670807d0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -832,7 +832,7 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
default:
- Op->dump(&DAG);
+ Op->print(errs(), &DAG);
llvm_unreachable("Custom lowering code for this"
"instruction is not implemented yet!");
break;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
index 7d56355074b..140fd4fc988 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -162,7 +162,7 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
C.emitError("Illegal instruction detected: " + Err);
- MI->dump();
+ MI->print(errs());
}
if (MI->isBundle()) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
index b78777f391e..b928e887192 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
@@ -861,7 +861,7 @@ void AMDGPUPromoteAlloca::handleAlloca(AllocaInst &I) {
continue;
}
default:
- Intr->dump();
+ Intr->print(errs());
llvm_unreachable("Don't know how to promote alloca intrinsic use.");
}
}
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index d27e04fccfc..d77717e3ba2 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1255,7 +1255,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
switch (Opc) {
default:
- MI->dump();
+ MI->print(errs());
llvm_unreachable("Unsupported opcode for unwinding information");
case ARM::tPUSH:
// Special case here: no src & dst reg, but two extra imp ops.
@@ -1291,7 +1291,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
int64_t Offset = 0;
switch (Opc) {
default:
- MI->dump();
+ MI->print(errs());
llvm_unreachable("Unsupported opcode for unwinding information");
case ARM::MOVr:
case ARM::tMOVr:
@@ -1346,11 +1346,11 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
}
}
} else if (DstReg == ARM::SP) {
- MI->dump();
+ MI->print(errs());
llvm_unreachable("Unsupported opcode for unwinding information");
}
else {
- MI->dump();
+ MI->print(errs());
llvm_unreachable("Unsupported opcode for unwinding information");
}
}
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index 86d1cf3059c..46262fd138c 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -320,8 +320,9 @@ void ARMConstantIslands::verify() {
#endif
}
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// print block size and offset information - debugging
-void ARMConstantIslands::dumpBBs() {
+LLVM_DUMP_METHOD void ARMConstantIslands::dumpBBs() {
DEBUG({
for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
const BasicBlockInfo &BBI = BBInfo[J];
@@ -333,6 +334,7 @@ void ARMConstantIslands::dumpBBs() {
}
});
}
+#endif
bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
diff --git a/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp b/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp
index 811b71e308d..9705c8b718b 100644
--- a/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp
@@ -98,9 +98,11 @@ ARMConstantPoolValue::hasSameValue(ARMConstantPoolValue *ACPV) {
return false;
}
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void ARMConstantPoolValue::dump() const {
errs() << " " << *this;
}
+#endif
void ARMConstantPoolValue::print(raw_ostream &O) const {
if (Modifier) O << "(" << getModifierText() << ")";
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 194cc0fca80..2306b76cc57 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -8729,7 +8729,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
bool isThumb2 = Subtarget->isThumb2();
switch (MI.getOpcode()) {
default: {
- MI.dump();
+ MI.print(errs());
llvm_unreachable("Unexpected instr type to insert");
}
diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
index 12091449cc1..8772be9bba9 100644
--- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
+++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
@@ -138,7 +138,7 @@ void BPFDAGToDAGISel::Select(SDNode *Node) {
else
errs() << "Error: ";
errs() << "Unsupport signed division for DAG: ";
- Node->dump(CurDAG);
+ Node->print(errs(), CurDAG);
errs() << "Please convert to unsigned div/mod.\n";
break;
}
diff --git a/llvm/lib/Target/BPF/BPFMCInstLower.cpp b/llvm/lib/Target/BPF/BPFMCInstLower.cpp
index 1faa1c09765..c8528e86731 100644
--- a/llvm/lib/Target/BPF/BPFMCInstLower.cpp
+++ b/llvm/lib/Target/BPF/BPFMCInstLower.cpp
@@ -54,7 +54,7 @@ void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
MCOperand MCOp;
switch (MO.getType()) {
default:
- MI->dump();
+ MI->print(errs());
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
diff --git a/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp b/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
index a5dc002642c..9d8c29463bf 100644
--- a/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
@@ -109,7 +109,7 @@ void llvm::HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
switch (MO.getType()) {
default:
- MI->dump();
+ MI->print(errs());
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
index 2c937216d46..176d3f75e11 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -131,13 +131,15 @@ namespace {
INITIALIZE_PASS(HexagonSplitDoubleRegs, "hexagon-split-double",
"Hexagon Split Double Registers", false, false)
-void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os,
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
+LLVM_DUMP_METHOD void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os,
const USet &Part, const TargetRegisterInfo &TRI) {
dbgs() << '{';
for (auto I : Part)
dbgs() << ' ' << PrintReg(I, &TRI);
dbgs() << " }";
}
+#endif
bool HexagonSplitDoubleRegs::isInduction(unsigned Reg, LoopRegMap &IRM) const {
for (auto I : IRM) {
diff --git a/llvm/lib/Target/Lanai/LanaiMCInstLower.cpp b/llvm/lib/Target/Lanai/LanaiMCInstLower.cpp
index 39c633578d4..90ede6566ac 100644
--- a/llvm/lib/Target/Lanai/LanaiMCInstLower.cpp
+++ b/llvm/lib/Target/Lanai/LanaiMCInstLower.cpp
@@ -130,7 +130,7 @@ void LanaiMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
MCOp = LowerSymbolOperand(MO, GetConstantPoolIndexSymbol(MO));
break;
default:
- MI->dump();
+ MI->print(errs());
llvm_unreachable("unknown operand type");
}
diff --git a/llvm/lib/Target/MSP430/MSP430MCInstLower.cpp b/llvm/lib/Target/MSP430/MSP430MCInstLower.cpp
index 47b0e270c5b..e7716382b22 100644
--- a/llvm/lib/Target/MSP430/MSP430MCInstLower.cpp
+++ b/llvm/lib/Target/MSP430/MSP430MCInstLower.cpp
@@ -119,7 +119,7 @@ void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
MCOperand MCOp;
switch (MO.getType()) {
default:
- MI->dump();
+ MI->print(errs());
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
index 08b8ed31ccb..5fca5ff2831 100644
--- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
+++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
@@ -417,16 +417,16 @@ bool MipsConstantIslands::isOffsetInRange
return isOffsetInRange(UserOffset, TrialOffset,
U.getMaxDisp(), U.NegOk);
}
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// print block size and offset information - debugging
-void MipsConstantIslands::dumpBBs() {
- DEBUG({
- for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
- const BasicBlockInfo &BBI = BBInfo[J];
- dbgs() << format("%08x BB#%u\t", BBI.Offset, J)
- << format(" size=%#x\n", BBInfo[J].Size);
- }
- });
+LLVM_DUMP_METHOD void MipsConstantIslands::dumpBBs() {
+ for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
+ const BasicBlockInfo &BBI = BBInfo[J];
+ dbgs() << format("%08x BB#%u\t", BBI.Offset, J)
+ << format(" size=%#x\n", BBInfo[J].Size);
+ }
}
+#endif
/// Returns a pass that converts branches to long branches.
FunctionPass *llvm::createMipsConstantIslandPass() {
return new MipsConstantIslands();
diff --git a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
index e527b018d4f..541b98e01b9 100644
--- a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
@@ -148,7 +148,7 @@ void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
MCOperand MCOp;
switch (MO.getType()) {
default:
- MI->dump();
+ MI->print(errs());
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
assert(!MO.getSubReg() && "Subregs should be eliminated!");
diff --git a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
index bcf0b1a7381..d3434b77be8 100644
--- a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
+++ b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
@@ -522,7 +522,7 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() {
if (RelevantFunction) {
DEBUG(dbgs() << "Swap vector when first built\n\n");
- dumpSwapVector();
+ DEBUG(dumpSwapVector());
}
return RelevantFunction;
@@ -731,7 +731,7 @@ void PPCVSXSwapRemoval::recordUnoptimizableWebs() {
}
DEBUG(dbgs() << "Swap vector after web analysis:\n\n");
- dumpSwapVector();
+ DEBUG(dumpSwapVector());
}
// Walk the swap vector entries looking for swaps fed by permuting loads
@@ -951,77 +951,78 @@ bool PPCVSXSwapRemoval::removeSwaps() {
return Changed;
}
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
// For debug purposes, dump the contents of the swap vector.
-void PPCVSXSwapRemoval::dumpSwapVector() {
+LLVM_DUMP_METHOD void PPCVSXSwapRemoval::dumpSwapVector() {
for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
int ID = SwapVector[EntryIdx].VSEId;
- DEBUG(dbgs() << format("%6d", ID));
- DEBUG(dbgs() << format("%6d", EC->getLeaderValue(ID)));
- DEBUG(dbgs() << format(" BB#%3d", MI->getParent()->getNumber()));
- DEBUG(dbgs() << format(" %14s ",
- TII->getName(MI->getOpcode()).str().c_str()));
+ dbgs() << format("%6d", ID);
+ dbgs() << format("%6d", EC->getLeaderValue(ID));
+ dbgs() << format(" BB#%3d", MI->getParent()->getNumber());
+ dbgs() << format(" %14s ", TII->getName(MI->getOpcode()).str().c_str());
if (SwapVector[EntryIdx].IsLoad)
- DEBUG(dbgs() << "load ");
+ dbgs() << "load ";
if (SwapVector[EntryIdx].IsStore)
- DEBUG(dbgs() << "store ");
+ dbgs() << "store ";
if (SwapVector[EntryIdx].IsSwap)
- DEBUG(dbgs() << "swap ");
+ dbgs() << "swap ";
if (SwapVector[EntryIdx].MentionsPhysVR)
- DEBUG(dbgs() << "physreg ");
+ dbgs() << "physreg ";
if (SwapVector[EntryIdx].MentionsPartialVR)
- DEBUG(dbgs() << "partialreg ");
+ dbgs() << "partialreg ";
if (SwapVector[EntryIdx].IsSwappable) {
- DEBUG(dbgs() << "swappable ");
+ dbgs() << "swappable ";
switch(SwapVector[EntryIdx].SpecialHandling) {
default:
- DEBUG(dbgs() << "special:**unknown**");
+ dbgs() << "special:**unknown**";
break;
case SH_NONE:
break;
case SH_EXTRACT:
- DEBUG(dbgs() << "special:extract ");
+ dbgs() << "special:extract ";
break;
case SH_INSERT:
- DEBUG(dbgs() << "special:insert ");
+ dbgs() << "special:insert ";
break;
case SH_NOSWAP_LD:
- DEBUG(dbgs() << "special:load ");
+ dbgs() << "special:load ";
break;
case SH_NOSWAP_ST:
- DEBUG(dbgs() << "special:store ");
+ dbgs() << "special:store ";
break;
case SH_SPLAT:
- DEBUG(dbgs() << "special:splat ");
+ dbgs() << "special:splat ";
break;
case SH_XXPERMDI:
- DEBUG(dbgs() << "special:xxpermdi ");
+ dbgs() << "special:xxpermdi ";
break;
case SH_COPYWIDEN:
- DEBUG(dbgs() << "special:copywiden ");
+ dbgs() << "special:copywiden ";
break;
}
}
if (SwapVector[EntryIdx].WebRejected)
- DEBUG(dbgs() << "rejected ");
+ dbgs() << "rejected ";
if (SwapVector[EntryIdx].WillRemove)
- DEBUG(dbgs() << "remove ");
+ dbgs() << "remove ";
- DEBUG(dbgs() << "\n");
+ dbgs() << "\n";
// For no-asserts builds.
(void)MI;
(void)ID;
}
- DEBUG(dbgs() << "\n");
+ dbgs() << "\n";
}
+#endif
} // end default namespace
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index a38a4b30b77..8fa43141225 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -357,7 +357,7 @@ X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
const MachineOperand &MO) const {
switch (MO.getType()) {
default:
- MI->dump();
+ MI->print(errs());
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
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