diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PIC16/PIC16ISelLowering.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 42 |
2 files changed, 25 insertions, 22 deletions
diff --git a/llvm/lib/Target/PIC16/PIC16ISelLowering.cpp b/llvm/lib/Target/PIC16/PIC16ISelLowering.cpp index 80c8f99ce73..7871a73c7e4 100644 --- a/llvm/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/llvm/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -926,6 +926,7 @@ PIC16TargetLowering::LowerCallReturn(SDValue Op, SDValue Chain, SDValue InFlag, SelectionDAG &DAG) { CallSDNode *TheCall = dyn_cast<CallSDNode>(Op); + DebugLoc dl = TheCall->getDebugLoc(); // Currently handling primitive types only. They will come in // i8 parts unsigned RetVals = TheCall->getNumRetVals(); @@ -948,7 +949,7 @@ PIC16TargetLowering::LowerCallReturn(SDValue Op, SDValue Chain, for(unsigned i=0, Offset=0;i<RetVals;i++) { - LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, Tys, Chain, LdLo, LdHi, + LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi, DAG.getConstant(LdOffset + Offset, MVT::i8), InFlag); @@ -961,7 +962,7 @@ PIC16TargetLowering::LowerCallReturn(SDValue Op, SDValue Chain, // To return use MERGE_VALUES ResultVals.push_back(Chain); - SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size()); + SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl); return Res; } diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index b9bb322b839..135f5970311 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1262,7 +1262,7 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) { SDValue Ops[] = { CallResult.first, CallResult.second }; - return DAG.getMergeValues(Ops, 2); + return DAG.getMergeValues(Ops, 2, dl); } SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, @@ -2999,6 +2999,7 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); unsigned BitWidth = VT.getSizeInBits(); + DebugLoc dl = Op.getDebugLoc(); assert(Op.getNumOperands() == 3 && VT == Op.getOperand(1).getValueType() && "Unexpected SHL!"); @@ -3010,22 +3011,23 @@ SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { SDValue Amt = Op.getOperand(2); MVT AmtVT = Amt.getValueType(); - SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, + SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); - SDValue Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt); - SDValue Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1); - SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); - SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, + SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); + SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); + SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); + SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, DAG.getConstant(-BitWidth, AmtVT)); - SDValue Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5); - SDValue OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); - SDValue OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt); + SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); + SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); + SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); SDValue OutOps[] = { OutLo, OutHi }; - return DAG.getMergeValues(OutOps, 2); + return DAG.getMergeValues(OutOps, 2, dl); } SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && VT == Op.getOperand(1).getValueType() && @@ -3038,18 +3040,18 @@ SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { SDValue Amt = Op.getOperand(2); MVT AmtVT = Amt.getValueType(); - SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, + SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); - SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); - SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); - SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); - SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, + SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); + SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); + SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); + SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, DAG.getConstant(-BitWidth, AmtVT)); - SDValue Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5); - SDValue OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); - SDValue OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt); + SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); + SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); + SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); SDValue OutOps[] = { OutLo, OutHi }; - return DAG.getMergeValues(OutOps, 2); + return DAG.getMergeValues(OutOps, 2, dl); } SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { @@ -3078,7 +3080,7 @@ SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), Tmp4, Tmp6, ISD::SETLE); SDValue OutOps[] = { OutLo, OutHi }; - return DAG.getMergeValues(OutOps, 2); + return DAG.getMergeValues(OutOps, 2, dl); } //===----------------------------------------------------------------------===// |
