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-rw-r--r--llvm/lib/Target/AArch64/AArch64InstrInfo.cpp36
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp40
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.cpp12
-rw-r--r--llvm/lib/Target/X86/X86FloatingPoint.cpp3
4 files changed, 56 insertions, 35 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 0395c48272a..29ddd6fb1a2 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1880,39 +1880,45 @@ void AArch64InstrInfo::storeRegToStackSlot(
else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasNEON() &&
"Unexpected register store without NEON");
- Opc = AArch64::ST1Twov1d, Offset = false;
+ Opc = AArch64::ST1Twov1d;
+ Offset = false;
}
break;
case 24:
if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasNEON() &&
"Unexpected register store without NEON");
- Opc = AArch64::ST1Threev1d, Offset = false;
+ Opc = AArch64::ST1Threev1d;
+ Offset = false;
}
break;
case 32:
if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasNEON() &&
"Unexpected register store without NEON");
- Opc = AArch64::ST1Fourv1d, Offset = false;
+ Opc = AArch64::ST1Fourv1d;
+ Offset = false;
} else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasNEON() &&
"Unexpected register store without NEON");
- Opc = AArch64::ST1Twov2d, Offset = false;
+ Opc = AArch64::ST1Twov2d;
+ Offset = false;
}
break;
case 48:
if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasNEON() &&
"Unexpected register store without NEON");
- Opc = AArch64::ST1Threev2d, Offset = false;
+ Opc = AArch64::ST1Threev2d;
+ Offset = false;
}
break;
case 64:
if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasNEON() &&
"Unexpected register store without NEON");
- Opc = AArch64::ST1Fourv2d, Offset = false;
+ Opc = AArch64::ST1Fourv2d;
+ Offset = false;
}
break;
}
@@ -1978,39 +1984,45 @@ void AArch64InstrInfo::loadRegFromStackSlot(
else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasNEON() &&
"Unexpected register load without NEON");
- Opc = AArch64::LD1Twov1d, Offset = false;
+ Opc = AArch64::LD1Twov1d;
+ Offset = false;
}
break;
case 24:
if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasNEON() &&
"Unexpected register load without NEON");
- Opc = AArch64::LD1Threev1d, Offset = false;
+ Opc = AArch64::LD1Threev1d;
+ Offset = false;
}
break;
case 32:
if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasNEON() &&
"Unexpected register load without NEON");
- Opc = AArch64::LD1Fourv1d, Offset = false;
+ Opc = AArch64::LD1Fourv1d;
+ Offset = false;
} else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasNEON() &&
"Unexpected register load without NEON");
- Opc = AArch64::LD1Twov2d, Offset = false;
+ Opc = AArch64::LD1Twov2d;
+ Offset = false;
}
break;
case 48:
if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasNEON() &&
"Unexpected register load without NEON");
- Opc = AArch64::LD1Threev2d, Offset = false;
+ Opc = AArch64::LD1Threev2d;
+ Offset = false;
}
break;
case 64:
if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasNEON() &&
"Unexpected register load without NEON");
- Opc = AArch64::LD1Fourv2d, Offset = false;
+ Opc = AArch64::LD1Fourv2d;
+ Offset = false;
}
break;
}
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 1eaa8118ba0..7e8fc3099f7 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3565,11 +3565,12 @@ void PPCDAGToDAGISel::PeepholeCROps() {
MVT::i1, MachineNode->getOperand(0),
MachineNode->getOperand(1).
getOperand(0));
- else if (AllUsersSelectZero(MachineNode))
+ else if (AllUsersSelectZero(MachineNode)) {
ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
MVT::i1, MachineNode->getOperand(0),
- MachineNode->getOperand(1)),
+ MachineNode->getOperand(1));
SelectSwap = true;
+ }
break;
case PPC::CRNAND:
if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
@@ -3603,11 +3604,12 @@ void PPCDAGToDAGISel::PeepholeCROps() {
MVT::i1, MachineNode->getOperand(1).
getOperand(0),
MachineNode->getOperand(0));
- else if (AllUsersSelectZero(MachineNode))
+ else if (AllUsersSelectZero(MachineNode)) {
ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
MVT::i1, MachineNode->getOperand(0),
- MachineNode->getOperand(1)),
+ MachineNode->getOperand(1));
SelectSwap = true;
+ }
break;
case PPC::CROR:
if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
@@ -3635,11 +3637,12 @@ void PPCDAGToDAGISel::PeepholeCROps() {
MVT::i1, MachineNode->getOperand(0),
MachineNode->getOperand(1).
getOperand(0));
- else if (AllUsersSelectZero(MachineNode))
+ else if (AllUsersSelectZero(MachineNode)) {
ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
MVT::i1, MachineNode->getOperand(0),
- MachineNode->getOperand(1)),
+ MachineNode->getOperand(1));
SelectSwap = true;
+ }
break;
case PPC::CRXOR:
if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
@@ -3674,11 +3677,12 @@ void PPCDAGToDAGISel::PeepholeCROps() {
MVT::i1, MachineNode->getOperand(0),
MachineNode->getOperand(1).
getOperand(0));
- else if (AllUsersSelectZero(MachineNode))
+ else if (AllUsersSelectZero(MachineNode)) {
ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
MVT::i1, MachineNode->getOperand(0),
- MachineNode->getOperand(1)),
+ MachineNode->getOperand(1));
SelectSwap = true;
+ }
break;
case PPC::CRNOR:
if (Op1Set || Op2Set)
@@ -3707,11 +3711,12 @@ void PPCDAGToDAGISel::PeepholeCROps() {
MVT::i1, MachineNode->getOperand(1).
getOperand(0),
MachineNode->getOperand(0));
- else if (AllUsersSelectZero(MachineNode))
+ else if (AllUsersSelectZero(MachineNode)) {
ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
MVT::i1, MachineNode->getOperand(0),
- MachineNode->getOperand(1)),
+ MachineNode->getOperand(1));
SelectSwap = true;
+ }
break;
case PPC::CREQV:
if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
@@ -3746,11 +3751,12 @@ void PPCDAGToDAGISel::PeepholeCROps() {
MVT::i1, MachineNode->getOperand(0),
MachineNode->getOperand(1).
getOperand(0));
- else if (AllUsersSelectZero(MachineNode))
+ else if (AllUsersSelectZero(MachineNode)) {
ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
MVT::i1, MachineNode->getOperand(0),
- MachineNode->getOperand(1)),
+ MachineNode->getOperand(1));
SelectSwap = true;
+ }
break;
case PPC::CRANDC:
if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
@@ -3781,11 +3787,12 @@ void PPCDAGToDAGISel::PeepholeCROps() {
MVT::i1, MachineNode->getOperand(0),
MachineNode->getOperand(1).
getOperand(0));
- else if (AllUsersSelectZero(MachineNode))
+ else if (AllUsersSelectZero(MachineNode)) {
ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
MVT::i1, MachineNode->getOperand(1),
- MachineNode->getOperand(0)),
+ MachineNode->getOperand(0));
SelectSwap = true;
+ }
break;
case PPC::CRORC:
if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
@@ -3816,11 +3823,12 @@ void PPCDAGToDAGISel::PeepholeCROps() {
MVT::i1, MachineNode->getOperand(0),
MachineNode->getOperand(1).
getOperand(0));
- else if (AllUsersSelectZero(MachineNode))
+ else if (AllUsersSelectZero(MachineNode)) {
ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
MVT::i1, MachineNode->getOperand(1),
- MachineNode->getOperand(0)),
+ MachineNode->getOperand(0));
SelectSwap = true;
+ }
break;
case PPC::SELECT_I4:
case PPC::SELECT_I8:
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 149cc4dbea0..50739421f3d 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -883,8 +883,8 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
if (PPC::CRBITRCRegClass.contains(SrcReg) &&
PPC::GPRCRegClass.contains(DestReg)) {
unsigned CRReg = getCRFromCRBit(SrcReg);
- BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
- .addReg(CRReg), getKillRegState(KillSrc);
+ BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
+ getKillRegState(KillSrc);
// Rotate the CR bit in the CR fields to be the least significant bit and
// then mask with 0x1 (MB = ME = 31).
BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
@@ -895,13 +895,13 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
return;
} else if (PPC::CRRCRegClass.contains(SrcReg) &&
PPC::G8RCRegClass.contains(DestReg)) {
- BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg)
- .addReg(SrcReg), getKillRegState(KillSrc);
+ BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
+ getKillRegState(KillSrc);
return;
} else if (PPC::CRRCRegClass.contains(SrcReg) &&
PPC::GPRCRegClass.contains(DestReg)) {
- BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
- .addReg(SrcReg), getKillRegState(KillSrc);
+ BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
+ getKillRegState(KillSrc);
return;
}
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index 97bb8ab653a..3718ac5dd27 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -1542,7 +1542,8 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
// Remove the operand so that later passes don't see it.
MI->RemoveOperand(i);
- --i, --e;
+ --i;
+ --e;
}
// We may have been carrying spurious live-ins, so make sure only the returned
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