diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a55770ae2f1..9d9ee212bbf 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23602,6 +23602,22 @@ static SDValue LowerBITCAST(SDValue Op, const X86Subtarget &Subtarget, MVT SrcVT = Op.getOperand(0).getSimpleValueType(); MVT DstVT = Op.getSimpleValueType(); + // Legalize (v64i1 (bitcast i64 (X))) by splitting the i64, bitcasting each + // half to v32i1 and concatenating the result. + if (SrcVT == MVT::i64 && DstVT == MVT::v64i1) { + assert(!Subtarget.is64Bit() && "Expected 32-bit mode"); + assert(Subtarget.hasBWI() && "Expected BWI target"); + SDValue Op0 = Op->getOperand(0); + SDLoc dl(Op); + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op0, + DAG.getIntPtrConstant(0, dl)); + Lo = DAG.getBitcast(MVT::v32i1, Lo); + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op0, + DAG.getIntPtrConstant(1, dl)); + Hi = DAG.getBitcast(MVT::v32i1, Hi); + return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi); + } + if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8 || SrcVT == MVT::i64) { assert(Subtarget.hasSSE2() && "Requires at least SSE2!"); |
