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-rw-r--r--llvm/lib/Target/AMDGPU/GCNILPSched.cpp2
-rw-r--r--llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp2
-rw-r--r--llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp8
-rw-r--r--llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp14
-rw-r--r--llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp7
-rw-r--r--llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp5
6 files changed, 17 insertions, 21 deletions
diff --git a/llvm/lib/Target/AMDGPU/GCNILPSched.cpp b/llvm/lib/Target/AMDGPU/GCNILPSched.cpp
index 651091d4413..d62dc8d8678 100644
--- a/llvm/lib/Target/AMDGPU/GCNILPSched.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNILPSched.cpp
@@ -335,7 +335,7 @@ GCNILPScheduler::schedule(ArrayRef<const SUnit*> BotRoots,
assert(C);
AvailQueue.remove(*C);
auto SU = C->SU;
- LLVM_DEBUG(dbgs() << "Selected "; SU->dump(&DAG));
+ LLVM_DEBUG(dbgs() << "Selected "; DAG.dumpNode(*SU));
advanceToCycle(SU->getHeight());
diff --git a/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
index 192d534bb9c..ec6bcae3355 100644
--- a/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
@@ -258,7 +258,7 @@ GCNMinRegScheduler::schedule(ArrayRef<const SUnit*> TopRoots,
assert(C);
RQ.remove(*C);
auto SU = C->SU;
- LLVM_DEBUG(dbgs() << "Selected "; SU->dump(&DAG));
+ LLVM_DEBUG(dbgs() << "Selected "; DAG.dumpNode(*SU));
releaseSuccessors(SU, StepNo);
Schedule.push_back(SU);
diff --git a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
index a1429a2ac50..478a473a51b 100644
--- a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
@@ -127,13 +127,13 @@ SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
LLVM_DEBUG(if (SU) {
dbgs() << " ** Pick node **\n";
- SU->dump(DAG);
+ DAG->dumpNode(*SU);
} else {
dbgs() << "NO NODE \n";
for (unsigned i = 0; i < DAG->SUnits.size(); i++) {
const SUnit &S = DAG->SUnits[i];
if (!S.isScheduled)
- S.dump(DAG);
+ DAG->dumpNode(S);
}
});
@@ -188,11 +188,11 @@ isPhysicalRegCopy(MachineInstr *MI) {
}
void R600SchedStrategy::releaseTopNode(SUnit *SU) {
- LLVM_DEBUG(dbgs() << "Top Releasing "; SU->dump(DAG););
+ LLVM_DEBUG(dbgs() << "Top Releasing "; DAG->dumpNode(*SU));
}
void R600SchedStrategy::releaseBottomNode(SUnit *SU) {
- LLVM_DEBUG(dbgs() << "Bottom Releasing "; SU->dump(DAG););
+ LLVM_DEBUG(dbgs() << "Bottom Releasing "; DAG->dumpNode(*SU));
if (isPhysicalRegCopy(SU->getInstr())) {
PhysicalRegCopy.push_back(SU);
return;
diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
index 18754442898..6670def7d09 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
@@ -471,7 +471,7 @@ void SIScheduleBlock::releaseSucc(SUnit *SU, SDep *SuccEdge) {
#ifndef NDEBUG
if (SuccSU->NumPredsLeft == 0) {
dbgs() << "*** Scheduling failed! ***\n";
- SuccSU->dump(DAG);
+ DAG->dumpNode(*SuccSU);
dbgs() << " has been released too many times!\n";
llvm_unreachable(nullptr);
}
@@ -611,13 +611,11 @@ void SIScheduleBlock::printDebug(bool full) {
dbgs() << "\nInstructions:\n";
if (!Scheduled) {
- for (SUnit* SU : SUnits) {
- SU->dump(DAG);
- }
+ for (const SUnit* SU : SUnits)
+ DAG->dumpNode(*SU);
} else {
- for (SUnit* SU : SUnits) {
- SU->dump(DAG);
- }
+ for (const SUnit* SU : SUnits)
+ DAG->dumpNode(*SU);
}
dbgs() << "///////////////////////\n";
@@ -1933,7 +1931,7 @@ void SIScheduleDAGMI::schedule()
LLVM_DEBUG(dbgs() << "Preparing Scheduling\n");
buildDAGWithRegPressure();
- LLVM_DEBUG(for (SUnit &SU : SUnits) SU.dumpAll(this));
+ LLVM_DEBUG(dump());
topologicalSort();
findRootsAndBiasEdges(TopRoots, BotRoots);
diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
index 74c550ce822..ebfe21bd17d 100644
--- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
@@ -215,8 +215,7 @@ void VLIWMachineScheduler::schedule() {
++su) if (SUnits[su].getDepth() > maxD) maxD =
SUnits[su].getDepth();
dbgs() << "Max Depth " << maxD << "\n";);
- LLVM_DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) SUnits[su]
- .dumpAll(this));
+ LLVM_DEBUG(dump());
initQueues(TopRoots, BotRoots);
@@ -489,7 +488,7 @@ void ConvergingVLIWScheduler::traceCandidate(const char *Label,
else
dbgs() << " ";
dbgs() << "cost(" << Cost << ")\t";
- SU->dump(DAG);
+ DAG->dumpNode(*SU);
}
// Very detailed queue dump, to be used with higher verbosity levels.
@@ -982,7 +981,7 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) {
<< " Scheduling instruction in cycle "
<< (IsTopNode ? Top.CurrCycle : Bot.CurrCycle) << " ("
<< reportPackets() << ")\n";
- SU->dump(DAG));
+ DAG->dumpNode(*SU));
return SU;
}
diff --git a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index 793a4dd7f62..cf3547f3cfb 100644
--- a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -180,9 +180,8 @@ void PPCDispatchGroupSBHazardRecognizer::EmitInstruction(SUnit *SU) {
CurGroup.clear();
CurSlots = CurBranches = 0;
} else {
- LLVM_DEBUG(dbgs() << "**** Adding to dispatch group: SU(" << SU->NodeNum
- << "): ");
- LLVM_DEBUG(DAG->dumpNode(SU));
+ LLVM_DEBUG(dbgs() << "**** Adding to dispatch group: ");
+ LLVM_DEBUG(DAG->dumpNode(*SU));
unsigned NSlots;
bool MustBeFirst = mustComeFirst(MCID, NSlots);
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