diff options
Diffstat (limited to 'llvm/lib/Target')
20 files changed, 32 insertions, 69 deletions
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 145ffef6f6f..3375e7c895f 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -251,7 +251,6 @@ static MCDisassembler *createAArch64Disassembler(const Target &T, DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &OS, raw_ostream &CS) const { CommentStream = &CS; diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.h b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.h index 2ba5a695701..374a89edcb7 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.h +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.h @@ -25,8 +25,7 @@ public: MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, - uint64_t Address, raw_ostream &VStream, - raw_ostream &CStream) const override; + uint64_t Address, raw_ostream &CStream) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 9388592c887..968d653bd74 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -268,7 +268,6 @@ static bool isValidDPP8(const MCInst &MI) { DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes_, uint64_t Address, - raw_ostream &WS, raw_ostream &CS) const { CommentStream = &CS; bool IsSDWA = false; diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h index c5eaba615c2..f975af409a0 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h @@ -53,7 +53,7 @@ public: DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &WS, raw_ostream &CS) const override; + raw_ostream &CS) const override; const char* getRegClassName(unsigned RegClassID) const; diff --git a/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp b/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp index 82da18617b9..5fae456c569 100644 --- a/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp +++ b/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp @@ -42,7 +42,6 @@ public: DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; }; @@ -297,7 +296,6 @@ static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn, DecodeStatus ARCDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &vStream, raw_ostream &cStream) const { MCDisassembler::DecodeStatus Result; if (Bytes.size() < 2) { diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index eabc26d05f4..62f506445ba 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -137,18 +137,15 @@ public: DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; private: DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const; DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const; mutable ITStatus ITBlock; @@ -576,8 +573,7 @@ static MCDisassembler *createARMDisassembler(const Target &T, // Post-decoding checks static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, - uint64_t Address, raw_ostream &OS, - raw_ostream &CS, + uint64_t Address, raw_ostream &CS, uint32_t Insn, DecodeStatus Result) { switch (MI.getOpcode()) { @@ -609,17 +605,16 @@ static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, - uint64_t Address, raw_ostream &OS, + uint64_t Address, raw_ostream &CS) const { if (STI.getFeatureBits()[ARM::ModeThumb]) - return getThumbInstruction(MI, Size, Bytes, Address, OS, CS); - return getARMInstruction(MI, Size, Bytes, Address, OS, CS); + return getThumbInstruction(MI, Size, Bytes, Address, CS); + return getARMInstruction(MI, Size, Bytes, Address, CS); } DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &OS, raw_ostream &CS) const { CommentStream = &CS; @@ -642,7 +637,7 @@ DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; - return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); + return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); } struct DecodeTable { @@ -673,7 +668,7 @@ DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; - return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); + return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); } Size = 4; @@ -906,7 +901,6 @@ void ARMDisassembler::UpdateThumbVFPPredicate( DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &OS, raw_ostream &CS) const { CommentStream = &CS; @@ -1010,7 +1004,7 @@ DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, if (Result != MCDisassembler::Fail) { Size = 4; Check(Result, AddThumbPredicate(MI)); - return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); + return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); } if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp index e203a5069c8..6d5466eb306 100644 --- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp +++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp @@ -40,7 +40,6 @@ public: DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; }; } @@ -114,7 +113,6 @@ static const uint8_t *getDecoderTable(uint64_t Size) { DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const { uint32_t Insn; diff --git a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp index c845524ad65..e3d783b1d82 100644 --- a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp +++ b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp @@ -67,7 +67,6 @@ public: DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; uint8_t getInstClass(uint64_t Inst) const { return (Inst >> 56) & 0x7; }; @@ -162,7 +161,6 @@ static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address, DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const { bool IsLittleEndian = getContext().getAsmInfo()->isLittleEndian(); uint64_t Insn, Hi; diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 99e3ee87157..d3fac9175b3 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -53,11 +53,9 @@ public: DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream, - bool &Complete) const; + raw_ostream &CStream, bool &Complete) const; DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; void remapInstruction(MCInst &Instr) const; }; @@ -166,7 +164,6 @@ extern "C" void LLVMInitializeHexagonDisassembler() { DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &os, raw_ostream &cs) const { DecodeStatus Result = DecodeStatus::Success; bool Complete = false; @@ -179,7 +176,7 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (Bytes.size() < HEXAGON_INSTR_SIZE) return MCDisassembler::Fail; MCInst *Inst = new (getContext()) MCInst; - Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); + Result = getSingleInstruction(*Inst, MI, Bytes, Address, cs, Complete); MI.addOperand(MCOperand::createInst(Inst)); Size += HEXAGON_INSTR_SIZE; Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); @@ -290,9 +287,11 @@ static void adjustDuplex(MCInst &MI, MCContext &Context) { } } -DecodeStatus HexagonDisassembler::getSingleInstruction( - MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &os, raw_ostream &cs, bool &Complete) const { +DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB, + ArrayRef<uint8_t> Bytes, + uint64_t Address, + raw_ostream &cs, + bool &Complete) const { assert(Bytes.size() >= HEXAGON_INSTR_SIZE); uint32_t Instruction = support::endian::read32le(Bytes.data()); diff --git a/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp b/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp index 25ae7c52170..2633ba63185 100644 --- a/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp +++ b/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp @@ -128,9 +128,10 @@ static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { } } -DecodeStatus LanaiDisassembler::getInstruction( - MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream & /*VStream*/, raw_ostream & /*CStream*/) const { +DecodeStatus +LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef<uint8_t> Bytes, uint64_t Address, + raw_ostream & /*CStream*/) const { uint32_t Insn; DecodeStatus Result = readInstruction32(Bytes, Size, Insn); diff --git a/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h b/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h index ae821df303d..6ca9b1df86c 100644 --- a/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h +++ b/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h @@ -28,8 +28,7 @@ public: // getInstruction - See MCDisassembler. MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, - uint64_t Address, raw_ostream &VStream, - raw_ostream &CStream) const override; + uint64_t Address, raw_ostream &CStream) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp b/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp index 59c12e24e8b..a32fbc99024 100644 --- a/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp +++ b/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp @@ -32,17 +32,14 @@ namespace { class MSP430Disassembler : public MCDisassembler { DecodeStatus getInstructionI(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const; DecodeStatus getInstructionII(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const; DecodeStatus getInstructionCJ(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const; public: @@ -51,7 +48,6 @@ public: DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; }; } // end anonymous namespace @@ -233,7 +229,6 @@ static const uint8_t *getDecoderTable(AddrMode SrcAM, unsigned Words) { DecodeStatus MSP430Disassembler::getInstructionI(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const { uint64_t Insn = support::endian::read16le(Bytes.data()); AddrMode SrcAM = DecodeSrcAddrModeI(Insn); @@ -289,7 +284,6 @@ DecodeStatus MSP430Disassembler::getInstructionI(MCInst &MI, uint64_t &Size, DecodeStatus MSP430Disassembler::getInstructionII(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const { uint64_t Insn = support::endian::read16le(Bytes.data()); AddrMode SrcAM = DecodeSrcAddrModeII(Insn); @@ -345,7 +339,6 @@ static MSP430CC::CondCodes getCondCode(unsigned Cond) { DecodeStatus MSP430Disassembler::getInstructionCJ(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const { uint64_t Insn = support::endian::read16le(Bytes.data()); unsigned Cond = fieldFromInstruction(Insn, 10, 3); @@ -367,7 +360,6 @@ DecodeStatus MSP430Disassembler::getInstructionCJ(MCInst &MI, uint64_t &Size, DecodeStatus MSP430Disassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const { if (Bytes.size() < 2) { Size = 0; @@ -378,10 +370,10 @@ DecodeStatus MSP430Disassembler::getInstruction(MCInst &MI, uint64_t &Size, unsigned Opc = fieldFromInstruction(Insn, 13, 3); switch (Opc) { case 0: - return getInstructionII(MI, Size, Bytes, Address, VStream, CStream); + return getInstructionII(MI, Size, Bytes, Address, CStream); case 1: - return getInstructionCJ(MI, Size, Bytes, Address, VStream, CStream); + return getInstructionCJ(MI, Size, Bytes, Address, CStream); default: - return getInstructionI(MI, Size, Bytes, Address, VStream, CStream); + return getInstructionI(MI, Size, Bytes, Address, CStream); } } diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 1623bc687b3..a858c6d1ca4 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -72,7 +72,6 @@ public: DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; }; @@ -1220,7 +1219,6 @@ static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const { uint32_t Insn; DecodeStatus Result; diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp index 3597fd15eeb..935fa066244 100644 --- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -34,7 +34,6 @@ public: DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; }; } // end anonymous namespace @@ -323,7 +322,7 @@ static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, - uint64_t Address, raw_ostream &OS, + uint64_t Address, raw_ostream &CS) const { // Get the four bytes of the instruction. Size = 4; @@ -350,4 +349,3 @@ DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); } - diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 15943ba4215..072ebd65ba7 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -38,7 +38,6 @@ public: DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; }; } // end anonymous namespace @@ -315,7 +314,6 @@ static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &OS, raw_ostream &CS) const { // TODO: This will need modification when supporting instruction set // extensions with instructions > 32-bits (up to 176 bits wide). diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp index bee331874e9..87eb77a4664 100644 --- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -36,7 +36,6 @@ public: DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; }; } @@ -332,7 +331,6 @@ static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const { uint32_t Insn; bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian(); diff --git a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp index 70c26db33ce..95a804cf803 100644 --- a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp +++ b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp @@ -34,7 +34,6 @@ public: DecodeStatus getInstruction(MCInst &instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; }; @@ -449,7 +448,6 @@ static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &OS, raw_ostream &CS) const { // Get the first two bytes of the instruction. Size = 0; diff --git a/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp b/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp index 9a9c31cff2d..46869f1700b 100644 --- a/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp +++ b/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp @@ -45,11 +45,9 @@ class WebAssemblyDisassembler final : public MCDisassembler { DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; DecodeStatus onSymbolStart(StringRef Name, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; public: @@ -123,7 +121,7 @@ bool parseImmediate(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes) { MCDisassembler::DecodeStatus WebAssemblyDisassembler::onSymbolStart( StringRef Name, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const { + raw_ostream &CStream) const { Size = 0; if (Address == 0) { // Start of a code section: we're parsing only the function count. @@ -158,7 +156,7 @@ MCDisassembler::DecodeStatus WebAssemblyDisassembler::onSymbolStart( MCDisassembler::DecodeStatus WebAssemblyDisassembler::getInstruction( MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t /*Address*/, - raw_ostream & /*OS*/, raw_ostream &CS) const { + raw_ostream &CS) const { CommentStream = &CS; Size = 0; int Opc = nextByte(Bytes, Size); diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index ad3255b8a28..be03dd77745 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -140,7 +140,6 @@ public: public: DecodeStatus getInstruction(MCInst &instr, uint64_t &size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &vStream, raw_ostream &cStream) const override; private: @@ -175,7 +174,7 @@ X86GenericDisassembler::X86GenericDisassembler( MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction( MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const { + raw_ostream &CStream) const { CommentStream = &CStream; InternalInstruction InternalInstr; diff --git a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index ff3d41fd527..159415fb445 100644 --- a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -37,7 +37,6 @@ public: DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const override; }; } @@ -735,9 +734,10 @@ DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, return S; } -MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction( - MCInst &instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &vStream, raw_ostream &cStream) const { +MCDisassembler::DecodeStatus +XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size, + ArrayRef<uint8_t> Bytes, uint64_t Address, + raw_ostream &cStream) const { uint16_t insn16; if (!readInstruction16(Bytes, Address, Size, insn16)) { |
